公开(公告)号：US07949907B2

公开(公告)日：2011-05-24

申请号：US11538072

申请日：2006-10-03

Applicant: Vijay Kumar Kodavalla ,  Chiranjeev Acharya

Inventor： Vijay Kumar Kodavalla ,  Chiranjeev Acharya

IPC: G06K5/04

CPC classification number: H03K19/1774 ,  H03K19/17744

Abstract: A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The device further comprises a control unit for generating control signal/s for selecting one of the inputs of the multiplexer and/or one of the outputs of the de-multiplexer. The control unit includes inputs for receiving a first clock signal, a second clock signal and indicators, said indicators being indicative of a phase skew relation amongst the clock signals. The control unit being configured for generating adaptively adjusted control signal/s according to the clock signals and indicators, said control signal/s are adaptively adjusted for eliminating impact of the phase skew amongst the clock signals.

Abstract translation: 提出了一种可编程逻辑器件。 该装置包括多个逻辑元件和多个I / O引脚; 多路复用器和/或解复用器单元。 多路复用器和/或多路复用器单元耦合在所述逻辑元件和I / O引脚之间。 该装置还包括一个控制单元，用于产生用于选择多路复用器的输入之一和/或解复用器的输出之一的控制信号。 控制单元包括用于接收第一时钟信号，第二时钟信号和指示符的输入，所述指示符指示时钟信号之间的相位偏移关系。 控制单元被配置为根据时钟信号和指示器产生自适应调整的控制信号，所述控制信号被自适应地调整，以消除时钟信号之间的相位偏移的影响。

公开(公告)号：US20080092001A1

公开(公告)日：2008-04-17

申请号：US11538072

申请日：2006-10-03

Applicant: Vijay Kumar Kodavalla ,  Chiranjeev Acharya

Inventor： Vijay Kumar Kodavalla ,  Chiranjeev Acharya

IPC: G01R31/28

CPC classification number: H03K19/1774 ,  H03K19/17744

Abstract: A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The device further comprises a control unit for generating control signal/s for selecting one of the inputs of the multiplexer and/or one of the outputs of the de-multiplexer. The control unit includes inputs for receiving a first clock signal, a second clock signal and indicators, said indicators being indicative of a phase skew relation amongst the clock signals. The control unit being configured for generating adaptively adjusted control signals according to the clock signals and indicators, said control signal's are adaptively adjusted for eliminating impact of the phase skew amongst the clock signals.

Abstract translation: 提出了一种可编程逻辑器件。 该装置包括多个逻辑元件和多个I / O引脚; 多路复用器和/或解复用器单元。 多路复用器和/或多路复用器单元耦合在所述逻辑元件和I / O引脚之间。 该装置还包括一个控制单元，用于产生用于选择多路复用器的输入之一和/或解复用器的输出之一的控制信号。 控制单元包括用于接收第一时钟信号，第二时钟信号和指示符的输入，所述指示符指示时钟信号之间的相位偏移关系。 控制单元被配置为根据时钟信号和指示器产生自适应调整的控制信号，所述控制信号被自适应地调整，以消除时钟信号之间的相位偏移的影响。