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公开(公告)号：US07747425B1
公开(公告)日：2010-06-29
申请号：US11593729
申请日：2006-11-07
申请人： Vipin Kumar Tiwari , Manish Bhatia , Abhijit Ray
发明人： Vipin Kumar Tiwari , Manish Bhatia , Abhijit Ray
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A peak current modeling method and system for modeling peak current demand of an integrated circuit (IC) block such as, e.g., a compilable memory instance. A current demand curve associated with the IC for a particular IC block event is obtained via simulation, for example. A defined time region associated with the particular IC block event is divided into multiple time segments, whereupon at least a first current value and a second current value for each time segment is obtained based on the current demand curve. Thereafter, the current demand curve is approximated, on a segment-by-segment basis, using a select approximate waveform depending on a relationship between the first and second current values.
摘要翻译： 用于建模集成电路（IC）块的峰值电流需求的峰值电流建模方法和系统，例如可编译存储器实例。 例如，通过模拟获得与特定IC块事件的IC相关联的电流需求曲线。 与特定IC块事件相关联的定义的时间区域被划分为多个时间段，因此基于当前需求曲线获得每个时间段的至少第一当前值和第二电流值。 此后，根据第一和第二电流值之间的关系，使用选择近似波形，逐段地逐次地近似当前需求曲线。
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公开(公告)号：US08004310B1
公开(公告)日：2011-08-23
申请号：US12125063
申请日：2008-05-22
申请人： Vipin Kumar Tiwari
发明人： Vipin Kumar Tiwari
IPC分类号： H03B1/00
CPC分类号： H03K19/0016
摘要： Power supply regulation. A power supply regulation system includes a transistor through which power is carried. The system also includes a switch connected to a gate of the transistor. Further, the system includes a transmission gate responsive to an input signal to apply a first signal level causing the transistor to enter an ON state in which the transistor carries full power, to apply a second signal level causing the transistor to enter an OFF state in which the transistor carries no power and to apply a third signal level causing the transistor to enter an INTERMEDIATE state in which the amount of power the transistor carries is controlled by the switch.
摘要翻译： 电源调节。 电源调节系统包括通过其承载电力的晶体管。 该系统还包括连接到晶体管的栅极的开关。 此外，该系统包括响应于输入信号的传输门，以施加第一信号电平，使得晶体管进入晶体管承载全部功率的导通状态，以施加使晶体管进入截止状态的第二信号电平 晶体管不传输电力并施加第三信号电平，使晶体管进入中间状态，其中晶体管承载的功率量由开关控制。
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3.发明授权公开(公告)号：US07549136B2
公开(公告)日：2009-06-16
申请号：US11614133
申请日：2006-12-22
申请人： Vipin Kumar Tiwari
发明人： Vipin Kumar Tiwari
CPC分类号： G06F17/5036
摘要： A system, method, and computer program product for approximating intrinsic capacitance of an integrated circuit (IC) block such as, for example, a compliable memory instance. Estimates of N-well capacitance, metal grid capacitance, and non-switching circuitry capacitance associated with the IC block are obtained. A total intrinsic capacitance of the IC block is then estimated based on the aforesaid constituent estimates.
摘要翻译： 一种用于近似诸如可编译存储器实例的集成电路（IC）块的固有电容的系统，方法和计算机程序产品。 获得与IC块相关联的N阱电容，金属栅极电容和非开关电路电容的估计。 然后基于上述成分估计值估计IC块的总固有电容。
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4.发明授权Method and system for securing data in a multi-time programmable non-volatile memory device 有权用于在多时间可编程非易失性存储器件中保护数据的方法和系统公开(公告)号：US07142452B1
公开(公告)日：2006-11-28
申请号：US11077654
申请日：2005-03-10
申请人： Vipin Kumar Tiwari
发明人： Vipin Kumar Tiwari
IPC分类号： G11C16/04
CPC分类号： G11C16/22 , G06F21/79 , H01L27/11521
摘要： A method and system for storing secure data in a multi-time programmable, non-volatile electrically-alterable memory device are disclosed. Accordingly, in an embodiment, a memory device may include a data register with a fixed N-bit pattern, comparator logic, control logic, and an array of non-volatile electrically-alterable memory cells. Each memory cell includes a floating gate to store an electronic charge representing the logical state of the memory cell. The plurality of memory cells may be logically partitioned to include an N-bit secure lock and a plurality of memory cells for storing secure data. The random bit values stored in the N-bit secure lock are read, and compared with the fixed N-bit pattern stored in the data register. If the N-bit patterns do not match, the control logic allows the plurality of memory cells for storing secure data to be programmed with secure data.
摘要翻译： 公开了一种用于将安全数据存储在多时间可编程的非易失性电可变存储器件中的方法和系统。 因此，在一个实施例中，存储器件可以包括具有固定N位模式的数据寄存器，比较器逻辑，控制逻辑和非易失性电可变存储器单元的阵列。 每个存储单元包括浮动门，用于存储表示存储器单元的逻辑状态的电子电荷。 多个存储器单元可以被逻辑地分区以包括N位安全锁和用于存储安全数据的多个存储单元。 读取存储在N位安全锁中的随机位值，并与存储在数据寄存器中的固定N位模式进行比较。 如果N位模式不匹配，则控制逻辑允许用存储安全数据的多个存储器单元用安全数据进行编程。
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5.发明申请公开(公告)号：US20070162879A1
公开(公告)日：2007-07-12
申请号：US11614133
申请日：2006-12-22
申请人： Vipin Kumar Tiwari
发明人： Vipin Kumar Tiwari
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system, method, and computer program product for approximating intrinsic capacitance of an integrated circuit (IC) block such as, for example, a compilable memory instance. Estimates of N-well capacitance, metal grid capacitance, and non-switching circuitry capacitance associated with the IC block are obtained. A total intrinsic capacitance of the IC block is then estimated based on the aforesaid constituent estimates.
摘要翻译： 一种用于近似诸如可编译存储器实例的集成电路（IC）块的固有电容的系统，方法和计算机程序产品。 获得与IC块相关联的N阱电容，金属栅极电容和非开关电路电容的估计。 然后基于上述成分估计值估计IC块的总固有电容。
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公开(公告)号：US07184346B1
公开(公告)日：2007-02-27
申请号：US11029916
申请日：2005-01-04
摘要： Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.
摘要翻译： 存储器使用降噪电路来感测存储器单元组的各种方法，装置和系统。 存储器具有被组织成存储器单元组的多个存储单元。 噪声降低电路在基本相同的时间对第一组存储器单元执行感测操作。 噪声降低电路基本上同时对第二组存储器单元执行读出操作。 噪声降低电路具有定时电路，用于在第一组的感测发起之后但在第一组存储器单元上的感测操作完成之前感测第二组存储器单元。
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公开(公告)号：US06850446B1
公开(公告)日：2005-02-01
申请号：US10226380
申请日：2002-08-22
摘要： Various methods, apparatuses and systems in which a memory uses a noise reduction circuit to sense groups of memory cells. The memory has a plurality of memory cells organized into groups of memory cells. The noise reduction circuit performs a sense operation on a first group of memory cells at the substantially the same time. The noise reduction circuit performs a sense operation on a second group of memory cells at substantially the same time. The noise reduction circuit has timing circuitry to sense the second group of memory cells after the sense of the first group initiates but prior to the completion of the sense operation on the first group of memory cells.
摘要翻译： 存储器使用降噪电路来感测存储器单元组的各种方法，装置和系统。 存储器具有被组织成存储器单元组的多个存储单元。 噪声降低电路在基本相同的时间对第一组存储器单元执行感测操作。 噪声降低电路基本上同时对第二组存储器单元执行读出操作。 噪声降低电路具有定时电路，用于在第一组的感测发起之后但在第一组存储器单元上的感测操作完成之前感测第二组存储器单元。
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