Method and apparatus for implementing a Viterbi decoder
    2.
    发明授权
    Method and apparatus for implementing a Viterbi decoder 有权
    用于实现维特比解码器的方法和装置

    公开(公告)号:US07173985B1

    公开(公告)日:2007-02-06

    申请号:US10212487

    申请日:2002-08-05

    IPC分类号: H04L27/06 H03M13/03

    摘要: The Viterbi decoder includes a branch metric processor that determines branch metrics for states of an encoder in a time period. The Viterbi decoder includes a survivor processor that selects survivor paths between states of the encoder in consecutive time periods. The Viterbi decoder includes a normalization unit that normalizes state metrics of the states of the encoder in the time period by subtracting a constant.

    摘要翻译: 维特比解码器包括分支度量处理器,其在一段时间段内确定编码器的状态的分支度量。 维特比解码器包括在连续时间段内选择编码器状态之间的幸存路径的幸存处理器。 维特比解码器包括归一化单元,其通过减去常数来对该时间段内的编码器的状态的状态度量进行归一化。