Calculator system
    1.
    发明授权
    Calculator system 失效
    计算机系统

    公开(公告)号:US3573746A

    公开(公告)日:1971-04-06

    申请号:US3573746D

    申请日:1968-12-09

    CPC classification number: G06F15/00

    Abstract: An electronic calculator system includes an arithmetic unit, an input register that receives signals from a keyboard and optionally from one or more card readers for transmission to the arithmetic unit and a memory unit. The card readers are pluggably connected in series and each includes interlock control which cooperates with a program counter to channel instruction and numerical data to the arithmetic unit from the card reader through the input register. The memory unit includes two reversible address counters which in conjunction with a program stored in a card reader enable efficient performance of mathematical manipulations of the matrix type.

    Programmable calculating apparatus
    2.
    发明授权
    Programmable calculating apparatus 失效
    可编程计算机

    公开(公告)号:US3428950A

    公开(公告)日:1969-02-18

    申请号:US3428950D

    申请日:1966-03-22

    Abstract: 1,160,612. Digital electric calculator. WANG LABORATORIES Inc. 13 March, 1967 [22 March, 1966 (2)], No. 11563/67. Heading G4A. A digital electric calculator apparatus comprises an arithmetic unit and first instruction supplying means including a plurality of manually operable keys and a second instruction supplying means including a record receiving device for receiving a record having data instructions encoded thereon in matrix fashion, a matrix of instruction sensors arranged in a series of groups, a plurality of sensor group actuators and a plurality of output lines, and first counting means to sequentially operate the sensor group actuators to provide instruction signals on the output lines. The calculator performs multiplication by forming the logarithm of a number, operating on the logarithm and producing an antilogarithm. A small store 166 contains the log. values of number 10,2,0À9,1À01, 0À999, 1À0001, the log. of a number entered in a work register 14 under the control of numeral keys 18 or a card reader 42 being formed by (a) sensing the position of a decimal point in register 22 and shifting the position to move it to the most significant stage and adding the value of log 10 to a zero value in a log register 28. (b) interrogating the most significant digit in register 14 to cause successive doubling of the number if the digit is a " 0 " or passing the number in register 14 through a delay circuit to divide by 10 and then subtracting from the original number to effectively multiply by 0À9 the two sequences causing log 2 to be subtracted from, and log 0À9 to be added to, the log register respectively. (c) when the most significant digit changes a " 1 " causes multiplication by 0À999 and a "0" causes multiplication by 1À0001 the appropriate logs being added or subtracted in the log. register. Card reader: read only memory.-Each card contains a matrix of prescored locations each of which may be removed by an operator to determine the appropriate instruction, each of 40 columns containing two six-bit words. The cards are placed in a card reader 42 (Fig. 2) having a base 69 carrying matrix 88 of kidneyshaped flat contacts and a cover 66 having pins 92 protruding through a matrix of holes in locations corresponding to the contacts of the base and the locations in the card. When any word is to be read the appropriate 6 bit column of the matrix 88 is energized. The punched locations in that column allow the signal to appear on pins 92. All the pins in each row are connected in series and to a corresponding set of pins in a further column 90 outside the area of the card. The energized pins in column 90 then energize contacts 86 in a column on the base 64 connected to a diode matrix to decode the signals. Two counters PC 30, DC 32 control the operation of reading the cards and performing the calculations. Program Counter 30 determines which column is read, and is normally incremented by 1 but may be jumped to provide a branching instruction. Decrement Counter 32 is normally decreased and used to determine the number of iterations that may be performed. A simple program read by the counters is described. The calculations are performed in serial fashion each bit being read into and combined in Adder Subtractors 110, 124, 162.

Patent Agency Ranking