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公开(公告)号：US20200212070A1
公开(公告)日：2020-07-02
申请号：US16462227
申请日：2018-09-17
Inventor： Guanghui HONG , Jingfeng XUE , Qiang GONG
IPC: H01L27/12
Abstract: A TFT array panel includes a primary display area and a slitting-edge display area. In the slitting-edge display area, a first metallic routing layer includes a first data line and a second metallic routing layer includes a first gate line. The first data line is connected to the second metallic routing layer through a hole in the interlayer dielectric layer so that the first data line overlaps the first gate line to form an overlapping capacitance to compensate for a gate line RC value.
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公开(公告)号：US20190385557A1
公开(公告)日：2019-12-19
申请号：US15745109
申请日：2017-11-27
Inventor： Guanghui HONG
IPC: G09G3/36
Abstract: The present application provides an NMOS type GOA circuit including: M cascaded GOA units, a Nth level GOA unit including: a forward reverse scan control circuit, a node signal control circuit, a node signal output circuit, a pull down circuit, and a output circuit; the forward reverse scan control circuit configured to perform a forward scan or a reverse scan according to a forward scan control signal or a reverse scan control signal; the output circuit including a first thin film transistor and a second thin film transistor, the node signal output circuit including a third thin film transistor, and the pull-down circuit including a fourth thin film transistor; wherein M≥N≥1, the high potential signal is a direct current signal, and the first and the drain terminal of the thin film transistor is one of a source and a drain, and the drain, the third terminal is a gate.
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公开(公告)号：US20190164855A1
公开(公告)日：2019-05-30
申请号：US15749444
申请日：2018-01-02
Inventor： Guanghui HONG , Qiang GONG
CPC classification number: H01L22/22 , G02F1/1309 , H01L21/485 , H01L21/76868 , H01L21/76894 , H01L22/14 , H01L27/124
Abstract: The present invention provides an array substrate and an repairing method thereof, wherein the array substrate includes adjacent two level GOA unit circuits, wherein an output terminal of a Nth level GOA unit circuit is connected to a Nth level gate line, an output terminal of a N+1th level GOA unit circuit is connected to a N+1th level gate line; and a repairing structure disposed between the Nth level gate line and the N+1th level gate line, the repairing structure configured to turn on the Nth level gate line and the N+1th level gate line by melting when the Nth level GOA unit circuit or the N+1th level GOA unit circuit damaged. A repairing structure is added between two adjacent gate lines, when a certain GOA unit circuit is damaged, the repairing structure is melted by a laser to make the adjacent two gate lines communicate with each other.
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公开(公告)号：US20190385958A1
公开(公告)日：2019-12-19
申请号：US15735931
申请日：2017-11-23
Inventor： Guanghui HONG
IPC: H01L23/60
Abstract: The disclosure discloses a display substrate, a display panel, and a display device. The display substrate includes: a substrate defining multiple panel areas; signal lines arranged in each of the panel areas; wherein at least part of the signal lines between at least two of the panel areas are connected. In the disclosure, at least part of the signal lines connected between the at least two panel areas are added on the display substrate. Therefore, through the connected signal lines, the different panel areas or display substrates may be conducted, may cooperate with each other to resist the electrostatic damage, thereby effectively improving the occurrence of the damage at the electrostatic discharge monitoring points when the ESD of the process occurs and improving the yield of the product.
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公开(公告)号：US20180190178A1
公开(公告)日：2018-07-05
申请号：US15316153
申请日：2016-11-04
Inventor： Guanghui HONG , Qiang GONG , Chunqian ZHANG
IPC: G09G3/20
CPC classification number: G09G3/2092 , G09G3/3266 , G09G3/3677 , G09G2310/0281 , G09G2310/0283 , G09G2310/0286 , G09G2310/0291 , G09G2310/061 , G09G2310/08 , G11C19/28 , H03K19/20
Abstract: The disclosure discloses a flat panel display device and a scan driving circuit thereof. The scan driving circuit includes a plurality of first scan drivers and a plurality of second scan drivers that are cascaded, the plurality of first scan drivers and the plurality of second scan drivers receive a clock signal alternately. The plurality of first scan drivers and the plurality of second scan drivers perform cascaded transmission according to the clock signal. The disclosure performs cascaded transmission by interposing a clock signal, which can reduce the amount of input signals and simplify the array process.
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Patent Agency Ranking
公开(公告)号：US20210358363A1
公开(公告)日：2021-11-18
申请号：US16477685
申请日：2019-01-22
Inventor： Guanghui HONG , Jingfeng XUE
IPC: G09G3/20
Abstract: A display panel is disclosed. The display panel includes a de-multiplexing switch group, a signal transmission line, a first control line, and a second control line. The first control line and the second control line are connected to the de-multiplexing switch group. Voltage levels of signals of the first control line and the second control line are opposite to each other, and a number of groups of the first control line and the second control line which intersect the signal transmission line is greater than or equal to zero. Pictures of display panels can be prevented from being affected by intersections of lines.
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7.发明申请公开(公告)号：US20200135070A1
公开(公告)日：2020-04-30
申请号：US15749422
申请日：2018-01-04
Inventor： Guanghui HONG
Abstract: A circuit and method for detecting pixel potential of a display panel and a display panel is provided. The circuit comprises a multiplexed output selector, at least one detection circuit and at least one signal amplifier. The detection circuit comprises a first TFT receiving a test signal and being connected to the multiplexed output selector. The multiplexed output selector is configured to selectively conduct the first data line, which is connected to a currently-detected sub-pixel unit, to the first TFT in accordance with a reverse clock signal to transmit a pixel potential signal of the currently-detected sub-pixel unit to the first TFT to control the first TFT to transmit the test signal to the signal amplifier. The signal amplifier is configured to receive and amplify the test signal to obtain and output a received signal. The present disclosure is able of measuring real pixel potential of the display panel.
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公开(公告)号：US20180211621A1
公开(公告)日：2018-07-26
申请号：US15321389
申请日：2016-10-12
Inventor： Qiang GONG , Gui CHEN , Guanghui HONG
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3696 , G09G2310/0286 , G09G2310/0291 , G09G2310/061
Abstract: A gate driver on array circuit includes a first driver module and a second driver module. The first driver module includes a first driver unit, a first output unit, and a first reset unit. The second driver module includes a second driver unit, a second output unit, and a second reset unit. The first output unit is used for generating a present stage scan drive signal and a present stage cascade signal. The second output unit is used for generating the present stage scan drive signal and the present stage cascade signal.
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公开(公告)号：US20180197491A1
公开(公告)日：2018-07-12
申请号：US15126409
申请日：2016-07-19
Inventor： Guanghui HONG , Qiang GONG
IPC: G09G3/36
CPC classification number: G09G3/3607 , G09G3/36 , G09G3/3659 , G09G3/3674 , G09G2300/0814 , G09G2310/0291
Abstract: A liquid crystal display comprises a demultiplexer (Demux). The demultiplexer for the display comprises an integrated circuit unit and a logic unit electrically connected to the integrated circuit unit. The integrated circuit unit outputs three pulse signals including a first pulse signal, a second pulse signal, and a third pulse signal. The logic unit transforms the three pulse signals having different high and low voltage levels into at least four control signals.
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公开(公告)号：US20200160805A1
公开(公告)日：2020-05-21
申请号：US16069273
申请日：2018-02-22
Inventor： Guanghui HONG
IPC: G09G3/36
Abstract: A GOA circuit includes an output module in which a second TFT is arranged. The second TFT has a drain connected to a source of a first TFT, a gate receiving a first control signal, and a source receiving an Mth clock signal. The first control signal controls the second TFT to turn on and off. Alternatively, the drain of the second TFT is connected to the source of the first TFT, the gate receiving the Mth clock signal and the source connected to the first node to allow the second TFT to be conducted on only when the Mth clock signal is a high voltage and the first node is of a high voltage and is cut off at the remaining time. It is possible to prevent a voltage difference from being induced between the source and drain of the first TFT to reduce the electric current stress.
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