公开(公告)号：US20060116394A1

公开(公告)日：2006-06-01

申请号：US11284660

申请日：2005-11-22

申请人： Walter Burgess ,  Dalia Jakas ,  William Huffman ,  William Miller ,  Kenneth Newlander ,  Mark Seefeld ,  Irene Uzinskas

发明人： Walter Burgess ,  Dalia Jakas ,  William Huffman ,  William Miller ,  Kenneth Newlander ,  Mark Seefeld ,  Irene Uzinskas

IPC分类号： A61K31/4745 ,  A61K31/4439 ,  A61K31/4433 ,  C07D471/02 ,  C07D405/02 ,  C07D403/02

CPC分类号： C07D213/73 ,  A61K31/16 ,  A61K31/381 ,  A61K31/416 ,  A61K31/47 ,  C07D401/12 ,  C07D401/14 ,  C07D403/12 ,  C07D405/12 ,  C07D471/04 ,  C07D487/04 ,  C07D491/04

摘要： Compounds are disclosed which are Fab I inhibitors and are useful in the treatment bacterial infections.

摘要翻译： 公开了作为Fab I抑制剂并且可用于治疗细菌感染的化合物。

公开(公告)号：US20060129787A1

公开(公告)日：2006-06-15

申请号：US11337440

申请日：2006-01-24

申请人： Timothy Hook ,  Peter Hsu ,  William Huffman ,  Henry Moreton ,  Earl Killian

发明人： Timothy Hook ,  Peter Hsu ,  William Huffman ,  Henry Moreton ,  Earl Killian

IPC分类号： G06F9/44

CPC分类号： G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/8084

摘要： The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

公开(公告)号：US20070250683A1

公开(公告)日：2007-10-25

申请号：US11702659

申请日：2007-02-06

申请人： Timothy Van Hook ,  Peter Hsu ,  William Huffman ,  Henry Moreton ,  Earl Killian

发明人： Timothy Van Hook ,  Peter Hsu ,  William Huffman ,  Henry Moreton ,  Earl Killian

IPC分类号： G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887

摘要： The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.