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公开(公告)号：US6134285A
公开(公告)日：2000-10-17
申请号：US864629
申请日：1997-05-28
申请人： Wei-Chi Lo
发明人： Wei-Chi Lo
摘要： In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register. In some embodiments of the data receiver an integer error compensation circuit compensates for the difference between the actual number of clock periods in a data period and the integer clock period count. A divider divides the integer clock period count to calculate an integer N and causes a data register to capture a data word on the N-th occurrence of an active edge of the clock signal after the beginning of the data word.
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公开(公告)号：US08942144B2
公开(公告)日：2015-01-27
申请号：US13106471
申请日：2011-05-12
申请人： Wei-Chieh Chang , Wei-Chi Lo , Charng-Show Li , Menping Chang
发明人： Wei-Chieh Chang , Wei-Chi Lo , Charng-Show Li , Menping Chang
CPC分类号： H04L5/16 , H04L5/1423 , H04L12/12 , H04L12/1881 , Y02D50/40 , Y02D50/42
摘要： An energy efficient Ethernet physical layer (PHY) device including an EEE control module configured to generate a control signal to transition the PHY device into a low power consumption mode based an operating condition, and a pause frame generator module responsive to the control signals to generate a pause frame. The pause frame generator module is configured to send the pause frame to a media access control (MAC) device to reduce an incoming flow of data packets from the MAC device to the PHY device for a pause time duration. In operation, the pause frame generator module generates the pause frame including a pause time indicating the length of time for the PHY device to be in the low power consumption mode. The value of the pause time for each pause frame is determined adaptively based on the amount of data traffic to be transmitted from the PHY device.
摘要翻译： 一种能量效率以太网物理层（PHY）设备，包括EEE控制模块，其被配置为基于操作条件生成控制信号以将PHY设备转换为低功耗模式;以及暂停帧发生器模块，其响应于所述控制信号而产生 一个暂停框架。 暂停帧生成器模块被配置为将暂停帧发送到媒体访问控制（MAC）设备，以在暂停时间段内减少从MAC设备到PHY设备的数据分组的传入流。 在操作中，暂停帧发生器模块产生暂停帧，其包括指示PHY设备处于低功耗模式的时间长度的暂停时间。 基于要从PHY设备发送的数据流量的量来自适应地确定每个暂停帧的暂停时间的值。
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公开(公告)号：US20120287829A1
公开(公告)日：2012-11-15
申请号：US13106471
申请日：2011-05-12
申请人： Wei-Chieh Chang , Wei-Chi Lo , Charng-Show Li , Menping Chang
发明人： Wei-Chieh Chang , Wei-Chi Lo , Charng-Show Li , Menping Chang
IPC分类号： H04L5/16
CPC分类号： H04L5/16 , H04L5/1423 , H04L12/12 , H04L12/1881 , Y02D50/40 , Y02D50/42
摘要： An energy efficient Ethernet physical layer (PHY) device including an EEE control module configured to generate a control signal to transition the PHY device into a low power consumption mode based an operating condition, and a pause frame generator module responsive to the control signals to generate a pause frame. The pause frame generator module is configured to send the pause frame to a media access control (MAC) device to reduce an incoming flow of data packets from the MAC device to the PHY device for a pause time duration. In operation, the pause frame generator module generates the pause frame including a pause time indicating the length of time for the PHY device to be in the low power consumption mode. The value of the pause time for each pause frame is determined adaptively based on the amount of data traffic to be transmitted from the PHY device.
摘要翻译： 一种能量效率以太网物理层（PHY）设备，包括EEE控制模块，其被配置为基于操作条件生成控制信号以将PHY设备转换为低功耗模式;以及暂停帧发生器模块，其响应于所述控制信号而产生 一个暂停框架。 暂停帧生成器模块被配置为将暂停帧发送到媒体访问控制（MAC）设备，以在暂停时间段内减少来自MAC设备到PHY设备的数据分组的传入流。 在操作中，暂停帧发生器模块产生暂停帧，其包括指示PHY设备处于低功耗模式的时间长度的暂停时间。 基于要从PHY设备发送的数据流量的量来自适应地确定每个暂停帧的暂停时间的值。
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公开(公告)号：US06359943B1
公开(公告)日：2002-03-19
申请号：US09460538
申请日：1999-12-13
申请人： Wei-Chi Lo
发明人： Wei-Chi Lo
IPC分类号： H04L704
摘要： In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register. In some embodiments of the data receiver an integer error compensation circuit compensates for the difference between the actual number of clock periods in a data period and the integer clock period count. A divider divides the integer clock period count to calculate an integer N and causes a data register to capture a data word on the N-th occurrence of an active edge of the clock signal after the beginning of the data word.
摘要翻译： 根据本发明，数据接收机的数据采集电路从与数据接收机的系统时钟不同的相位或频率工作的数据发射机的数据流捕获数据。 在一个实施例中，数据接收器确定数据流的数据周期中时钟信号的时钟周期数。 具体地，信号检测电路接收具有周期性和独特特征的信号。 周期和特征的周期与固定比例因子与数据周期有关。 计数器对周期性特征特征的第一次出现与周期性特征特征的第二次出现之间的时钟信号的时钟周期数进行计数。 乘法器/除法器电路将第一计数器的内容除以倍数乘以缩放因子以确定整数时钟周期计数。 乘法或除法的结果存储在计数寄存器中。 在数据接收机的一些实施例中，整数误差补偿电路补偿数据周期中的实际时钟周期数与整数时钟周期计数之间的差异。 分频器将整数时钟周期计数器除以计算整数N，并使数据寄存器在数据字开始之后的时钟信号的有效沿的第N次发生时捕获数据字。
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