公开(公告)号：US08533577B1

公开(公告)日：2013-09-10

申请号：US13555860

申请日：2012-07-23

申请人： Weishi Feng ,  Zhan Yu

发明人： Weishi Feng ,  Zhan Yu

IPC分类号： G06F11/00

CPC分类号： H03M5/145 ,  H03M13/09 ,  H03M13/27 ,  H04L1/0041 ,  H04L1/0061 ,  H04L1/0071

摘要： A data encoding system includes an interleaving module, a generating module, and an insertion module. The interleaving module is configured to receive a data stream. The data stream includes a plurality of data blocks. The interleaving module is configured to, for each data block of a selected subset of the plurality of data blocks, swap positions of a pair of adjacent bits of the data block. The generating module is configured to (i) receive the data stream and (ii) for each of the plurality of data blocks, generate at least one corresponding error checking bit. The insertion module is configured to (i) receive the plurality of data blocks as modified by the interleaving module and (ii) generate an output data stream by inserting the at least one corresponding error checking bit into each one of the plurality of data blocks received from the interleaving module.

摘要翻译： 数据编码系统包括交织模块，生成模块和插入模块。 交织模块被配置为接收数据流。 数据流包括多个数据块。 交织模块被配置为对于多个数据块的所选子集的每个数据块，数据块的一对相邻位的交换位置。 生成模块被配置为（i）接收数据流，并且（ii）对于多个数据块中的每一个，生成至少一个相应的错误校验位。 插入模块被配置为（i）接收由交织模块修改的多个数据块，并且（ii）通过将至少一个对应的错误校验位插入到所接收的多个数据块中的每一个中来生成输出数据流 从交织模块。

公开(公告)号：US08230314B1

公开(公告)日：2012-07-24

申请号：US12156649

申请日：2008-06-03

申请人： Weishi Feng ,  Zhan Yu

发明人： Weishi Feng ,  Zhan Yu

IPC分类号： G06F11/00

CPC分类号： H03M5/145 ,  H03M13/09 ,  H03M13/27 ,  H04L1/0041 ,  H04L1/0061 ,  H04L1/0071

摘要： A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.

摘要翻译： 用于数据流的数据编码系统包括交织模块，其将数据流接收为N位数据块，并且反转所选数据块的N位中的至少两个的位置。 生成模块为每个N位数据块生成P个错误校验位。 插入模块从生成模块接收P个错误校验位，并将P个错误校验位插入到从交错模块接收到的对应的数据块中。

公开(公告)号：US07312727B1

公开(公告)日：2007-12-25

申请号：US11786246

申请日：2007-04-11

申请人： Weishi Feng ,  Zhan Yu

发明人： Weishi Feng ,  Zhan Yu

IPC分类号： H03M5/00

CPC分类号： H04L1/0041 ,  G11B20/10

摘要： A communications channel comprises a seed selector that selectively removes X M-bit symbols of user data from a seed set comprising Y M-bit symbols and that selects a scrambling seed from Y-X symbols remaining in the seed set, where X, Y and M are integers greater than one. A Hamming weight coding device that determines a Hamming weight of symbols of scrambled user data that are generated based on the user data and the selected scrambling seed and that selectively codes the symbols depending upon the determined Hamming weight.

摘要翻译： 通信信道包括种子选择器，其选择性地从包含Y个M比特符号的种子集中删除用户数据的X M比特符号，并且从剩余在种子集中的YX符号中选择加扰种子，其中X，Y和M是 大于1的整数。 一种汉明权重编码装置，其确定基于用户数据和所选择的加扰种子生成的加扰用户数据的符号的汉明权重，并且根据所确定的汉明权重选择性地对符号进行编码。

公开(公告)号：US07310765B1

公开(公告)日：2007-12-18

申请号：US11049753

申请日：2005-02-04

申请人： Weishi Feng ,  Liang Zhang ,  Zhan Yu

发明人： Weishi Feng ,  Liang Zhang ,  Zhan Yu

IPC分类号： H03M13/23 ,  H03M13/29

CPC分类号： H03M13/091 ,  H03M13/29

摘要： A system for detecting errors in received input data includes a first error detection circuit. The first error detection circuit is configured to receive the input data. The input data includes at least one of data and data with errors. The first error detection circuit is configured to generate a first error detection sequence in a first order. The system includes a second error detection circuit. The second error detection circuit is configured to receive the first error detection sequence and an error sequence. The error sequence is received in a second order that is different from the first order when there is data with errors. The second error detection circuit is configured to generate a second error detection sequence that indicates whether the error sequence is generated correctly.

摘要翻译： 用于检测接收到的输入数据中的错误的系统包括第一错误检测电路。 第一错误检测电路被配置为接收输入数据。 输入数据包括具有错误的数据和数据中的至少一个。 第一错误检测电路被配置为以第一顺序生成第一错误检测序列。 该系统包括第二错误检测电路。 第二错误检测电路被配置为接收第一错误检测序列和错误序列。 当存在具有错误的数据时，以与第一顺序不同的第二顺序接收错误序列。 第二错误检测电路被配置为生成指示是否正确生成错误序列的第二错误检测序列。

公开(公告)号：US07234097B1

公开(公告)日：2007-06-19

申请号：US10701271

申请日：2003-11-04

申请人： Weishi Feng ,  Zhan Yu

发明人： Weishi Feng ,  Zhan Yu

IPC分类号： H03M13/00

CPC分类号： G11B20/1833 ,  G11B20/1866

摘要： A communications channel that receives a user data sequence including N symbols and that supports host CRC includes a host bus interface (HBI) that generates cyclic redundancy check (CRCU) bits based on the user data sequence. A data dependent scrambler (DDS) receives the user data sequence and the CRCU bits and generates a scrambling seed. The DDS generates a scrambled user data sequence that is based on the user data sequence and the scrambling seed and generates a difference sequence.

摘要翻译： 接收包括N个符号并且支持主机CRC的用户数据序列的通信信道包括基于用户数据序列生成循环冗余校验（CRC ）的主机总线接口（HBI）。 数据相关扰频器（DDS）接收用户数据序列和CRC <！ - SIPO - >位，并产生加扰种子。 DDS产生基于用户数据序列和加扰种子的加扰用户数据序列，并产生差分序列。

公开(公告)号：US07010739B1

公开(公告)日：2006-03-07

申请号：US10304511

申请日：2002-11-26

申请人： Weishi Feng ,  Zhan Yu

发明人： Weishi Feng ,  Zhan Yu

IPC分类号： H03M13/03

CPC分类号： H03M13/153 ,  H03M13/6502

摘要： An error correcting Reed-Solomon decoder includes a syndrome calculator that calculates syndrome values. An error locator polynomial generator communicates with the syndrome calculator and generates an error locator polynomial. An error location finder communicates with at least one of the syndrome calculator and the error locator polynomial generator and generates error locations. An error values finder communicates with at least one of the syndrome calculator, the error location finder and the error locator polynomial generator and generates error values using an error value relationship that is not based on the traditional error evaluator polynomial. The error locator polynomial generator is an inversionless Berlekamp-Massey algorithm (iBMA), which calculates an error locator polynomial and a scratch polynomial. The error value relationship is based on the error locator polynomial and the scratch polynomial.

摘要翻译： 纠错Reed-Solomon解码器包括计算综合征值的综合征计算器。 误差定位多项式生成器与校正子计算器进行通信，并生成错误定位器多项式。 错误定位器与错误定位器多项式发生器中的至少一个通信，并产生错误位置。 错误值查找器与错误计算器，错误定位器和错误定位器多项式生成器中的至少一个通信，并且使用不基于传统的误差评估器多项式的误差值关系来生成误差值。 误差定位多项式生成器是一种无倒数的Berlekamp-Massey算法（iBMA），它计算出一个误差定位多项式和一个划痕多项式。 误差值关系基于误差定位器多项式和临时多项式。

公开(公告)号：US07392464B1

公开(公告)日：2008-06-24

申请号：US10896726

申请日：2004-07-22

申请人： Weishi Feng ,  Zhan Yu

发明人： Weishi Feng ,  Zhan Yu

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： H03M5/145 ,  H03M13/09 ,  H03M13/27 ,  H04L1/0041 ,  H04L1/0061 ,  H04L1/0071

摘要： A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.

摘要翻译： 用于数据流的数据编码系统包括交织模块，其将数据流接收为N位数据块，并且反转所选数据块的N位中的至少两个的位置。 生成模块为每个N位数据块生成P个错误校验位。 插入模块从生成模块接收P个错误校验位，并将P个错误校验位插入到从交错模块接收到的对应的数据块中。

公开(公告)号：US07322004B1

公开(公告)日：2008-01-22

申请号：US11407436

申请日：2006-04-20

申请人： Zhan Yu ,  Weishi Feng

发明人： Zhan Yu ,  Weishi Feng

IPC分类号： H03M13/00

CPC分类号： H03M13/6502 ,  H03M13/1515 ,  H03M13/153 ,  H03M13/1555 ,  H03M13/1585

摘要： A Reed-Solomon decoder includes an inversionless Berlekamp-Massey algorithm (iBMA) circuit with a pipelined feedback loop. A first polynomial generator generates error locator polynomial values. A discrepancy generator generates discrepancy values based on the error locator polynomial values and the scratch polynomial values. Arithmetic units are used to generate the discrepancy values are also used to generate the error locator polynomial to reduce circuit area. A first delay circuit delays the discrepancy values. A feedback loop feeds back the delayed discrepancy values to the error locator polynomial generator. An error location finder circuit communicates with the iBMA circuit and identifies error locations. An error value computation circuit communicates with at least one of the error location finder circuit and the iBMA circuit and generates error values.

摘要翻译： Reed-Solomon解码器包括具有流水线反馈回路的无倒角Berlekamp-Massey算法（iBMA）电路。 第一个多项式生成器生成错误定位器多项式值。 差异发生器基于错误定位器多项式值和临时多项式值产生差异值。 用于产生差异值的算术单位也用于生成误差定位多项式以减少电路面积。 第一延迟电路延迟差异值。 反馈回路将延迟差值反馈给误差定位器多项式发生器。 错误定位器电路与iBMA电路通信并识别错误位置。 错误值计算电路与错误定位器电路和iBMA电路中的至少一个通信，并产生误差值。

公开(公告)号：US07218255B1

公开(公告)日：2007-05-15

申请号：US10639796

申请日：2003-08-12

申请人： Weishi Feng ,  Zhan Yu

发明人： Weishi Feng ,  Zhan Yu

IPC分类号： H03M5/00

CPC分类号： H04L1/0041 ,  G11B20/10

摘要： A communications channel includes a buffer that receives symbols of user data including a plurality of M-bit symbols. A seed selector receives the M-bit symbols of the user data, selectively removes symbols of the user data from a seed set, and selects a scrambling seed from symbols remaining in the seed set. A scrambling device that communicates with the seed selector and the data buffer generates scrambled user data using the user data and the selected scrambling seed. A Hamming weight coding device determines a Hamming weight of symbols of the scrambled user data and selectively codes the symbols depending upon the determined Hamming weight.

摘要翻译： 通信信道包括接收包括多个M位符号的用户数据的符号的缓冲器。 种子选择器接收用户数据的M位符号，从种子集合中选择性地去除用户数据的符号，并从剩余在种子集中的符号中选择加扰种子。 与种子选择器和数据缓冲器进行通信的加扰设备使用用户数据和所选择的加扰种子来生成加扰的用户数据。 汉明权重编码装置确定加扰的用户数据的符号的汉明权重，并根据确定的汉明权重选择性地编码符号。

公开(公告)号：US06662346B1

公开(公告)日：2003-12-09

申请号：US10072034

申请日：2002-02-08

申请人： Zhan Yu ,  Weishi Feng

发明人： Zhan Yu ,  Weishi Feng

IPC分类号： G06F1705

CPC分类号： G06F7/724 ,  G06F17/5045 ,  G06F2217/78

摘要： A finite field arithmetic circuit with reduced power dissipation has first and second circuit inputs. A first circuit transition probability of the first circuit input is calculated by applying a random input to the first circuit input and a constant input to the second circuit input. A second circuit transition probability of the second circuit input is calculated by applying a constant input to the first circuit input and a random input to the second circuit input. One of the first and second circuit inputs having a lower circuit transition probability is selected. A first time-varying rate that a first input signal to the arithmetic circuit varies is compared with a second time-varying rate that a second input signal to the arithmetic circuit varies. The input signal having a higher time-varying rate is selected and coupled to the selected one of the first and second circuit inputs.

摘要翻译： 具有降低功耗的有限域运算电路具有第一和第二电路输入。 通过将随机输入施加到第一电路输入和对第二电路输入的恒定输入来计算第一电路输入的第一电路转移概率。 通过将恒定输入施加到第一电路输入和对第二电路输入的随机输入来计算第二电路输入的第二电路转移概率。 选择具有较低电路转移概率的第一和第二电路输入之一。 将运算电路的第一输入信号变化的第一时变速率与运算电路的第二输入信号变化的第二时变速率进行比较。 具有较高时变速率的输入信号被选择并耦合到所选择的第一和第二电路输入中的一个。