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公开(公告)号：US11550658B1
公开(公告)日：2023-01-10
申请号：US17465165
申请日：2021-09-02
发明人： James J. Walsh , Stephen Gold , David R. Meyer , Vivek Shivhare
摘要： A storage system caches logical-to-physical address table entries read in volatile memory. The logical-to-physical address table entries are stored in codewords. The storage system can vary a number or size of an entry in a codeword. Additionally or alternatively, each codeword can store both complete and partial logical-to-physical address table entries. In one example, a codeword having 62 bytes of data and two bytes of error correction code stores 15 complete logical-to-physical address table entries and one partial logical-to-physical address table entry, where the remainder of the partial entry is stored in another codeword. This configuration strikes a good balance between storage space efficiency and random-access write performance.
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公开(公告)号：US10372346B2
公开(公告)日：2019-08-06
申请号：US15662170
申请日：2017-07-27
摘要： A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.
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公开(公告)号：US11704023B2
公开(公告)日：2023-07-18
申请号：US17700362
申请日：2022-03-21
CPC分类号： G06F3/0613 , G06F3/0607 , G06F3/0659 , G06F3/0664 , G06F3/0683 , G06F3/0688 , G06F13/102 , G06F13/4045 , Y02D10/00
摘要： A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.
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公开(公告)号：US20180032267A1
公开(公告)日：2018-02-01
申请号：US15662170
申请日：2017-07-27
CPC分类号： G06F3/0613 , G06F3/0607 , G06F3/0659 , G06F3/0664 , G06F3/0683 , G06F3/0688 , G06F13/102 , G06F13/4045 , Y02D10/14
摘要： A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.
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公开(公告)号：US11314418B2
公开(公告)日：2022-04-26
申请号：US17210277
申请日：2021-03-23
摘要： A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.
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公开(公告)号：US10990293B2
公开(公告)日：2021-04-27
申请号：US16821918
申请日：2020-03-17
摘要： A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.
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7.发明授权公开(公告)号：US09513831B2
公开(公告)日：2016-12-06
申请号：US14921418
申请日：2015-10-23
发明人： James J. Walsh , Andrew J. Tomlin
CPC分类号： G06F3/0625 , G06F3/06 , G06F3/061 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/1441 , G06F11/1471 , G06F11/1474 , G06F12/0246 , G06F12/1009 , G06F2212/1032 , G06F2212/657 , G06F2212/7201 , G06F2212/7207 , G06F2212/7208
摘要： Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated.
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8.发明授权Method and system for atomically writing scattered information in a solid state storage device 有权在固态存储设备中将散布信息原子地写入的方法和系统公开(公告)号：US09170938B1
公开(公告)日：2015-10-27
申请号：US14060547
申请日：2013-10-22
发明人： James J. Walsh , Andrew J. Tomlin
CPC分类号： G06F3/0625 , G06F3/06 , G06F3/061 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/1441 , G06F11/1471 , G06F11/1474 , G06F12/0246 , G06F12/1009 , G06F2212/1032 , G06F2212/657 , G06F2212/7201 , G06F2212/7207 , G06F2212/7208
摘要： Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated.
摘要翻译： 本文公开了用于处理到达分散地址范围的原子写入命令的若干方法和系统。 一个实施例包括在数据存储设备中执行操作的方法，所述方法包括：接收原子写命令; 获得受原子写入命令影响的多个逻辑地址范围; 对于多个受影响的范围中的每一个，分配元数据信息以跟踪在该范围执行的写入操作的完成; 在逻辑地址的范围内执行写操作; 在完成写入操作的范围内更新元数据信息; 并将更新推迟到数据存储设备的翻译图，直到元数据信息被更新为止。
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