公开(公告)号：US10552259B2

公开(公告)日：2020-02-04

申请号：US15922793

申请日：2018-03-15

Applicant: Western Digital Technologies, Inc.

Inventor： Adam Noah Jacobvitz ,  Gulzar Ahmed Kathawala ,  Kroum Stanimirov Stoev ,  Bin Wu

IPC: H03M13/00 ,  G06F11/10 ,  G11C16/26 ,  H03M13/29 ,  G11C29/52

Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform additional NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense.

公开(公告)号：US20190286516A1

公开(公告)日：2019-09-19

申请号：US15922793

申请日：2018-03-15

Applicant: Western Digital Technologies, Inc.

Inventor： Adam Noah Jacobvitz ,  Gulzar Ahmed Kathawala ,  Kroum Stanimirov Stoev ,  Bin Wu

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  G11C16/26

Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform addition NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense.