-
公开(公告)号：US10552259B2
公开(公告)日：2020-02-04
申请号：US15922793
申请日：2018-03-15
Applicant: Western Digital Technologies, Inc.
Inventor： Adam Noah Jacobvitz , Gulzar Ahmed Kathawala , Kroum Stanimirov Stoev , Bin Wu
Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform additional NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense.
-
公开(公告)号：US20190286516A1
公开(公告)日：2019-09-19
申请号：US15922793
申请日：2018-03-15
Applicant: Western Digital Technologies, Inc.
Inventor： Adam Noah Jacobvitz , Gulzar Ahmed Kathawala , Kroum Stanimirov Stoev , Bin Wu
Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller for decoding codewords during an error correction read recovery process. In illustrative examples, an iterative procedure exploits artificial codewords generated using information obtained from a NAND or other non-volatile memory (NVM) in a previous sense operation. That is, procedures are described that use information obtained in one stage of read recovery to facilitate a subsequent stage to reduce the need to perform addition NAND senses. In one example, information obtained from a sense operation performed for an initial hard bit decode is used in subsequent soft bit decodes. Moreover, iterative decoding procedures are provided that progressively increase correction strength. The procedures may alternate between hard and soft reads while using syndrome weight to determine a failed bit code gradient for identifying the sensing voltage for a next hard sense.
-
公开(公告)号：US10324859B2
公开(公告)日：2019-06-18
申请号：US15633388
申请日：2017-06-26
Applicant: Western Digital Technologies, Inc.
Inventor： Daniel Joseph Linnen , Ashish Ghai , Dongxiang Liao , Srikar Peesari , Avinash Rajagiri , Philip Reusswig , Bin Wu
IPC: G06F12/10 , G06F12/1036 , G06F3/06 , G06F11/10 , G06F11/14
Abstract: Certain apparatuses, systems, methods, and computer program products are used for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.
-
公开(公告)号：US20180373644A1
公开(公告)日：2018-12-27
申请号：US15633388
申请日：2017-06-26
Applicant: Western Digital Technologies, Inc.
Inventor： Daniel Joseph Linnen , Ashish Ghai , Dongxiang Liao , Srikar Peesari , Avinash Rajagiri , Philip Reusswig , Bin Wu
IPC: G06F12/1036 , G06F3/06 , G06F11/10 , G06F11/14 , G06F12/10
Abstract: Apparatuses, systems, methods, and computer program products are disclosed for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.
-
-
-
Search Results
4
records
(took 0.017 seconds)
