公开(公告)号：US20240079318A1

公开(公告)日：2024-03-07

申请号：US17903965

申请日：2022-09-06

申请人： Western Digital Technologies, Inc.

发明人： Md. Sayed Mobin ,  Nagesh Vodrahalli ,  Pranav Balachander ,  Narayanan Terizhandur V

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

CPC分类号： H01L23/5227 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/528 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48095 ,  H01L2224/48105 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1438 ,  H01L2924/30101 ,  H01L2924/30105 ,  H01L2924/30111

摘要： A storage device includes a substrate of a memory package and a first memory die. The substrate includes a controller and a first pin pad, the first pin pad being electrically connected to the controller and defining a data channel for data communications. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a redistribution layer electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.

公开(公告)号：US20240312916A1

公开(公告)日：2024-09-19

申请号：US18361168

申请日：2023-07-28

申请人： Western Digital Technologies, Inc.

发明人： Nagesh Vodrahalli ,  Chih-Yang Li ,  Shrikar Bhagath ,  Narayanan Terizhandur V

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/5384 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2924/1438

摘要： A semiconductor device package includes a substrate, a stack of memory dies positioned on the substrate, and an interposer spaced from the stack of memory dies and also positioned on the substrate. First and second sets of bond pads are electrically connected to the substrate, where the second set of bond pads is positioned on the interposer above the substrate. A first set of bond wires electrically connects a first sub-stack of the memory dies to the first set of bond pads. A second set of bond wires electrically connects a second sub-stack of memory dies, positioned above the first sub-stack, to the second set of bond wires. The first and second sub-stacks of memory dies may be electrically isolated from one another to reduce noise in electrical signals transmitted to and from the memory dies.