公开(公告)号：US20060031279A1

公开(公告)日：2006-02-09

申请号：US11175489

申请日：2005-07-06

申请人： Wilhelm Haller ,  Wen Li ,  Michael Kelly ,  Holger Wetter

发明人： Wilhelm Haller ,  Wen Li ,  Michael Kelly ,  Holger Wetter

IPC分类号： G06F7/50

CPC分类号： G06F7/494 ,  G06F7/508 ,  G06F7/575 ,  G06F2207/4924

摘要： An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data set, i.e., valid decimal data can be used and the non-existing decimal numbers (10 to 15) need not be excluded by separate check logic any more. This reduces the complexity of the logic functions.

摘要翻译： 一个加法器电路，用于将两个二进制或两个十进制操作数A和B相加，其中运算由输入操作数A和B直接计算而不加加6或减6运算到进位计算中。 对于所有时序关键功能，可以使用简化的输入数据集，即有效的十进制数据，并且不需要单独的检查逻辑排除不存在的十进制数（10至15）。 这降低了逻辑功能的复杂性。

公开(公告)号：US5944772A

公开(公告)日：1999-08-31

申请号：US970076

申请日：1997-11-13

申请人： Juergen Haas ,  Wilhelm Haller ,  Ulrich Krauch ,  Thomas Ludwig ,  Holger Wetter

发明人： Juergen Haas ,  Wilhelm Haller ,  Ulrich Krauch ,  Thomas Ludwig ,  Holger Wetter

IPC分类号： G06F7/50 ,  G06F7/575

CPC分类号： G06F7/575 ,  G06F7/507 ,  G06F7/508

摘要： A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Said bit function generator derives from the operands Ai and Bi bit functions Gi, Pi which are provided as logic function output and as input to said sum generator for producing preliminary arithmetic functions (SUM0, SUM1) to anticipate carry-in signals of one or zero. A result selector (70) is controlled by a byte position carry-out signal (Cy55) from the carry network means and by operation control signals to select from the output of said pre-sum logic one of the arithmetic functions (SUM0, SUM1) or one of the logic functions as result of the unit operation.

摘要翻译： 组合加法器和逻辑单元具有减小的运算和逻辑运算的运算延迟，并且如果在微处理器芯片的算术和逻辑部分中实现，则提供改进的风扇并降低布线延迟和容量。 该单元包括连接到操作数输入的进位网络（30），用于产生字节位置（By0-By7）的进位信号，并且还包括具有位函数发生器（42）的和和逻辑（32）和总和 发电机（45,46,48）。 所述比特函数发生器从作为逻辑功能输出提供的操作数Ai和Bi比特函数Gi，Pi导出，并作为用于产生预计算函数（SUM0，SUM1）的所述和发生器的输入，以预期一或零的进位信号 。 结果选择器（70）由来自携带网络装置的字节位置执行输出信号（Cy55）和操作控制信号控制，以从所述算术功能（SUM0，SUM1）之一的所述并行逻辑逻辑的输出中进行选择， 或作为单元操作的结果的逻辑功能之一。

公开(公告)号：US08286115B2

公开(公告)日：2012-10-09

申请号：US12330664

申请日：2008-12-09

申请人： Holger Wetter ,  Maarten Boersma ,  Wilhelm Haller ,  Armin Windschiegl

发明人： Holger Wetter ,  Maarten Boersma ,  Wilhelm Haller ,  Armin Windschiegl

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/66

摘要： A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.

摘要翻译： 一种用于创建集成电路（IC）的布局和接线图的系统包括配置成接收分级示意图并且创建放置的布局的布置引擎。 该系统还包括平面布局引擎，其被配置为接收分级示意图并且创建耦合到放置引擎和平面布局引擎的平面布局和后注释引擎，后注释引擎被配置为接收分层放置的布局和平面 未布置的布局，并从中创建一个平放布局。

公开(公告)号：US20100146471A1

公开(公告)日：2010-06-10

申请号：US12330664

申请日：2008-12-09

申请人： Holger Wetter ,  Maarten Boersma ,  Wilhelm Haller ,  Armin Windschiegl

发明人： Holger Wetter ,  Maarten Boersma ,  Wilhelm Haller ,  Armin Windschiegl

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/66

摘要： A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.

摘要翻译： 一种用于创建集成电路（IC）的布局和接线图的系统包括配置成接收分级示意图并且创建放置的布局的布置引擎。 该系统还包括平面布局引擎，其被配置为接收分级示意图并且创建耦合到放置引擎和平面布局引擎的平面布局和后注释引擎，后注释引擎被配置为接收分层放置的布局和平面 未布置的布局，并从中创建一个平放布局。

公开(公告)号：US06292819B1

公开(公告)日：2001-09-18

申请号：US09235028

申请日：1999-01-21

申请人： Wolfgang Bultmann ,  Wilhelm Haller ,  Holger Wetter ,  Alexander Wörner

发明人： Wolfgang Bultmann ,  Wilhelm Haller ,  Holger Wetter ,  Alexander Wörner

IPC分类号： G06F750

CPC分类号： G06F7/494 ,  G06F7/507 ,  G06F2207/4924

摘要： A binary and decimal adder unit uses a pre-sum logic for generating pre-sums of the operands A, B under the presumption of one and zero carry inputs into the decimal digit position, and also uses a digits carry network for generating binary carries within the decimal digit positions and a high order carry out signal of said plurality of decimal digits. Each decimal digit position of said adder unit provides a six correction and a pre-sum selection. The pre-sum logic comprises a carry prediction logic for generating decimal digit position carry out signals on the presumption of a zero carry input and of a one carry input into the decimal digit. In response to gating signals derived from the carry out signals of the carry prediction logic and operation control signals a pre-selection is performed for selecting a qualified pre-sum generated on the presumption of a zero carry input into the decimal digit, and for selecting a qualified pre-sum generated on the presumption of a one carry input into the decimal digit. The pre-selection of the qualified pre-sums is performed for all decimal digit positions in parallel to the generation and distribution of the carries in the digits carry network over the total of decimal digit positions. The pre-sum selection logic further comprises a two way selector which is responsive to a digit carry-in signal from the digits carry network for selecting one the qualified pre-sums as the correct sum of the digit position. According to one embodiment of the invention, the pre-sum logic generates six corrected pre-sums which are included in the pre-selection of qualified pre-sums.

摘要翻译： 二进制和十进制加法器单元使用预和逻辑来在将一个和零个进位输入推定为小数位置的情况下产生操作数A，B的前置和，并且还使用位数进位网络来产生二进制运算 所述十进位数字位置和所述多个十进制数字的高阶进位信号。 所述加法器单元的每个十进位数位置提供六次校正和一个预先和选择。 前和逻辑包括进位预测逻辑，用于在零进位输入和一个进位输入到十进制数的推定中产生十位数位置执行信号。 响应于来自进位预测逻辑的执行信号和操作控制信号的门控信号，执行预选择，以选择在零进位输入的推定中产生的合格的前置和十进制数，并且用于选择 根据对十进制数字的一个进位输入的推定产生合格的预先和。 对所有十进制数字位置进行合并预分配的预先选择，并行执行数字携带网络中携带的数据的生成和分配，总数小数位数。 预和选择逻辑还包括双向选择器，其响应于来自数字携带网络的数字进位信号，用于选择一个合格的前置和作为数字位置的正确和。 根据本发明的一个实施例，预先和逻辑产生六个经校正的前置和，其被包括在预先选择合格的前提中。

公开(公告)号：US5928319A

公开(公告)日：1999-07-27

申请号：US969244

申请日：1997-11-13

申请人： Wilhelm Haller ,  Ulrich Krauch ,  Thomas Ludwig ,  Holger Wetter

发明人： Wilhelm Haller ,  Ulrich Krauch ,  Thomas Ludwig ,  Holger Wetter

IPC分类号： G06F7/491 ,  G06F7/50

CPC分类号： G06F7/4912 ,  G06F7/507

摘要： A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.

摘要翻译： 组合的二进制/十进制加法器单元减少了处理二进制编码十进制操作数的操作延迟，并且允许使用组合的二进制/十进制加法单元的处理器单元的增加的周期速率。 对于加法器单元的十进制位数的总和的并行生成和分配，对于每个十进制数位置产生预和。 预计总和预期小数位置的进位，并且在产生了最高十进制位数的进位信号之后需要进行六次校正。 每个十进制位数的进位信号与操作控制信号组合使用，以选择数位位置的正确预置。

公开(公告)号：US20060179103A1

公开(公告)日：2006-08-10

申请号：US11054687

申请日：2005-02-09

申请人： Steven Carlough ,  Wilhelm Haller ,  Wen Li ,  Eric Schwarz

发明人： Steven Carlough ,  Wilhelm Haller ,  Wen Li ,  Eric Schwarz

IPC分类号： G06F7/50

CPC分类号： G06F7/4912 ,  G06F7/483 ,  G06F7/507

摘要： A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand. Output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first clock cycle. The system further includes an incrementer for adding one to each of the sums stored in the intermediate result register, the incrementing occurring during a second clock cycle. In addition, a mechanism is provided for selecting between each of the sums and the sums incremented by one. The input to the mechanism includes the carry chain. The output includes the final sum of the first operand and the second operand. The selecting occurs during the second clock cycle.

公开(公告)号：US08423940B2

公开(公告)日：2013-04-16

申请号：US13209504

申请日：2011-08-15

申请人： Lukas Daellenbach ,  Elmar Gaugler ,  Wilhelm Haller ,  Ralf Richter

发明人： Lukas Daellenbach ,  Elmar Gaugler ,  Wilhelm Haller ,  Ralf Richter

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/82

摘要： A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.

摘要翻译： 计算机化方法，数据处理系统和计算机程序产品减少已经放置和布线的电子电路的缓冲设计的噪声。 对于设计中功率条纹和接地条纹（半间隔）之间的所有区域，形状分为不同的关键级别。 形状根据其临界水平重新排列，使得具有更高临界水平的形状比具有较低临界水平的形状更靠近条纹。

公开(公告)号：US5964845A

公开(公告)日：1999-10-12

申请号：US765418

申请日：1996-12-16

申请人： Robert Braun ,  Wilhelm Haller ,  Klaus Jorg Getzlaff ,  Thomas Pfluger ,  Dietmar Schmunkamp

发明人： Robert Braun ,  Wilhelm Haller ,  Klaus Jorg Getzlaff ,  Thomas Pfluger ,  Dietmar Schmunkamp

IPC分类号： G06F15/78 ,  G06F13/42 ,  G06F11/00

CPC分类号： G06F13/4291

摘要： One or more processing units are connected with a clock component (comprising a clock) over a bi-directional serial link, and data frames are transmitted between the clock component and the processing units. The clock component may contain a serial link combination circuit for combining multiple processing unit serial links, operating in parallel, into a single serial link connected to the clock. Both of the clock component and the processing units contain an error detection and correction mechanism which examine and modify data within the data frames to perform error detection and correction. The clock component optionally contains an external interface for connection to a command-issuing Service Processor.

摘要翻译： PCT No.PCT / EP95 / 01451 Sec。 371日期1996年12月16日第 102（e）日期1996年12月16日PCT提交1995年4月18日PCT公布。 WO96 / 33464 PCT公开号 日期1996年10月24日一个或多个处理单元通过双向串行链路与时钟组件（包括时钟）连接，数据帧在时钟组件和处理单元之间传输。 时钟部件可以包含用于将并行操作的多个处理单元串行链路组合成连接到时钟的单个串行链路的串行链路组合电路。 时钟分量和处理单元都包含一个错误检测和校正机制，它检查和修改数据帧内的数据以执行错误检测和校正。 时钟组件可选地包含用于连接到命令发布服务处理器的外部接口。

公开(公告)号：US20090112963A1

公开(公告)日：2009-04-30

申请号：US11926582

申请日：2007-10-29

申请人： Wilhelm Haller ,  Guenter Mayer ,  Veit Gernhoefer ,  Ulrich Krauch ,  Simon Fabel

发明人： Wilhelm Haller ,  Guenter Mayer ,  Veit Gernhoefer ,  Ulrich Krauch ,  Simon Fabel

IPC分类号： G06F7/508

CPC分类号： G06F7/507

摘要： A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.

摘要翻译： 提供电路所在的方法，电路装置和设计结构，以通过将两个操作数细分为相等位数的组来执行二进制运算单元中的两个操作数的减法，通过适当的算术运算生成对 分别包含相同比特位置的两个操作数的特定的比特组的中间结果。 每个中间结果对的第一个中间结果是在“0”的进位假设下产生的，并且每个中间结果对的第二个中间结果在“1”的进位假设下生成。 选择来自每组比特的每个特定中间结果对的正确的中间结果，并且通过适当地合并所选择的正确的中间结果来生成两个操作数的减法的结果。