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公开(公告)号:US06774825B2
公开(公告)日:2004-08-10
申请号:US10253909
申请日:2002-09-25
IPC分类号: H03M700
CPC分类号: H03M13/27 , G11B20/1426 , G11B20/1833 , G11B20/1866 , H03M5/145
摘要: A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks sorted into interleaves. A second encoder encodes a subset of the input blocks to produce output blocks, where the first encoder permutates a remainder of the input blocks and the output blocks to produce a codeword.
摘要翻译: 基于ECC交错结构来调制编码的系统和方法包括编码包括被排序成交织的输入块的位的输入流的第一编码器。 第二编码器编码输入块的子集以产生输出块,其中第一编码器排列剩余的输入块和输出块以产生码字。
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公开(公告)号:US06934205B1
公开(公告)日:2005-08-23
申请号:US10363189
申请日:2000-09-06
申请人: Pramod Pandey , Ali Najafi
发明人: Pramod Pandey , Ali Najafi
CPC分类号: G06F11/27
摘要: A processor assisted memory BIST to identify detective memory addresses. The processor generates the address to be tested and the BIST generates the test data used to test the memory. Data is written to an read from memory. The read data is compared with the test data. If a mismatch occurs, the BIST generates an interrupt to identify the processor. Since the processor generated the address, the defective memory address is identified. The defective memory address can subsequently be replaced with redundant memory cells.
摘要翻译: 处理器辅助存储器BIST来识别检测存储器地址。 处理器生成要测试的地址,BIST生成用于测试内存的测试数据。 数据被写入从内存中读取。 将读取的数据与测试数据进行比较。 如果发生不匹配,BIST将产生一个中断来识别处理器。 由于处理器产生了地址,故障存储器地址被识别。 有缺陷的存储器地址随后可被替换为冗余存储器单元。
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公开(公告)号:US20170190139A1
公开(公告)日:2017-07-06
申请号:US15392330
申请日:2016-12-28
申请人: Atieh Haghdoost , Mehdi Kargar , Ali Najafi
发明人: Atieh Haghdoost , Mehdi Kargar , Ali Najafi
CPC分类号: B32B3/18 , B32B5/16 , B32B15/04 , B32B15/20 , C09D5/1681 , C23C30/00 , C25D3/22 , C25D3/38 , C25D5/18 , C25D5/48 , C25D5/50
摘要: Certain embodiments are described herein of coatings and articles comprising coatings. In some examples, the coating comprises a textured layer comprising at least one metal or metallic compound. The coating may also comprise a plurality of individual surface features in a micro- or nano-structure size range, wherein the plurality of surface features are positioned in different planes in different heights with respect to a reference zero point in the textured layer. In some instances, there is substantially no space between the plurality of surface features of the textured layer. Methods of producing the coatings are also described.
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