Bist for parallel testing of on chip memory
    2.
    发明授权
    Bist for parallel testing of on chip memory 有权
    双绞线用于片上存储器的并行测试

    公开(公告)号:US06934205B1

    公开(公告)日:2005-08-23

    申请号:US10363189

    申请日:2000-09-06

    IPC分类号: G06F11/27 G11C7/00

    CPC分类号: G06F11/27

    摘要: A processor assisted memory BIST to identify detective memory addresses. The processor generates the address to be tested and the BIST generates the test data used to test the memory. Data is written to an read from memory. The read data is compared with the test data. If a mismatch occurs, the BIST generates an interrupt to identify the processor. Since the processor generated the address, the defective memory address is identified. The defective memory address can subsequently be replaced with redundant memory cells.

    摘要翻译: 处理器辅助存储器BIST来识别检测存储器地址。 处理器生成要测试的地址,BIST生成用于测试内存的测试数据。 数据被写入从内存中读取。 将读取的数据与测试数据进行比较。 如果发生不匹配,BIST将产生一个中断来识别处理器。 由于处理器产生了地址,故障存储器地址被识别。 有缺陷的存储器地址随后可被替换为冗余存储器单元。