公开(公告)号：US07907359B2

公开(公告)日：2011-03-15

申请号：US12345561

申请日：2008-12-29

申请人： William G. Bliss ,  Razmik Karabed

发明人： William G. Bliss ,  Razmik Karabed

IPC分类号： G11B5/02 ,  G11B20/06 ,  G11B20/08 ,  G11B5/09 ,  G11B15/52 ,  G11B19/02 ,  G11B20/00

CPC分类号： G11B20/10194 ,  G11B20/10009 ,  G11B20/1426 ,  G11B20/1833 ,  G11B2220/2516

摘要： The invention relates to a data modulation method applicable to make data streams tend to have desired properties, useful for clock recovery, making signals more distinguishable, or enforcing run-length conditions. A stream of input data and a corresponding stream of output data are grouped into elements of a finite field. Input elements of said input data are modified by a transform generating output elements of the output data, such that a current output element is a linear combination of a current input element and at least one previous output element. A multiplier applied to at least one previous output element is a non-zero and non-unity element of the finite field. A set of initial conditions inherent to the transform, is selected such that the output elements resulting from the transform tend to have the desired property.

摘要翻译： 本发明涉及一种适用于使数据流倾向于具有期望属性的数据调制方法，对于时钟恢复有用，使得信号更可区分，或者执行运行长度条件。 输入数据流和相应的输出数据流被分组成有限域的元素。 通过产生输出数据的输出元件的变换来修改所述输入数据的输入元件，使得当前输出元件是当前输入元件和至少一个先前输出元件的线性组合。 应用于至少一个先前输出元素的乘数是有限域的非零和非单位元素。 选择变换固有的一组初始条件，使得由变换产生的输出元素倾向于具有期望的属性。

公开(公告)号：US07486456B2

公开(公告)日：2009-02-03

申请号：US11016283

申请日：2004-12-17

申请人： William G. Bliss ,  Razmik Karabed

发明人： William G. Bliss ,  Razmik Karabed

IPC分类号： G11B5/02 ,  G11B20/06 ,  G11B20/08 ,  G11B5/09 ,  G11B15/52 ,  G11B19/02 ,  G11B20/00

CPC分类号： G11B20/10194 ,  G11B20/10009 ,  G11B20/1426 ,  G11B20/1833 ,  G11B2220/2516

摘要： The invention relates to a data modulation method applicable to make data streams tend to have desired properties, useful for clock recovery, making signals more distinguishable, or enforcing run-length conditions. A stream of input data and a corresponding stream of output data are grouped into elements of a finite field. Input elements of said input data are modified by a transform generating output elements of the output data, such that a current output element is a linear combination of a current input element and at least one previous output element. A multiplier applied to at least one previous output element is a non-zero and non-unity element of the finite field. A set of initial conditions inherent to the transform, is selected such that the output elements resulting from the transform tend to have the desired property.

摘要翻译： 本发明涉及一种适用于使数据流倾向于具有期望属性的数据调制方法，对于时钟恢复有用，使得信号更可区分，或者执行运行长度条件。 输入数据流和相应的输出数据流被分组成有限域的元素。 通过产生输出数据的输出元件的变换来修改所述输入数据的输入元件，使得当前输出元件是当前输入元件和至少一个先前输出元件的线性组合。 应用于至少一个先前输出元素的乘数是有限域的非零和非单位元素。 选择变换固有的一组初始条件，使得由变换产生的输出元素倾向于具有期望的属性。

公开(公告)号：US07274312B2

公开(公告)日：2007-09-25

申请号：US11359453

申请日：2006-04-06

申请人： William G. Bliss ,  Andrei Vityaev ,  Razmik Karabed

发明人： William G. Bliss ,  Andrei Vityaev ,  Razmik Karabed

IPC分类号： H03M7/00

CPC分类号： G11B20/1426 ,  G11B20/10009 ,  G11B20/1833 ,  G11B2020/1446 ,  H03M5/145 ,  H03M13/093

摘要： An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b. . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.

摘要翻译： 一种装置具有转换电路，预编码器电路和选择电路。 转换电路转换用户数据b 1，b 2，b。 。 。 对于编码序列c 0，c 1，c 2，...， 。 。 c 。 选择电路在编码序列c 0 0，c 1，c 2 2中选择c <0> 0 。 。 。 使得预编码器电路的输出具有小于转换的最大数量q。 转换电路可以包括用于转换用户数据b 1，b 2，b 3 3的编码器电路。 。 。 c 到序列c 1，c 2。 。 。 以及向序列c 1，c 2 2加上c 0的转换最小化电路。 。 。 c 。 该装置可以具有电路，用于将至少一个额外的位（其可以是奇偶校验位）添加到编码序列c 0，c 1，c 2 。 。 。 c 。

公开(公告)号：US07137056B2

公开(公告)日：2006-11-14

申请号：US10253903

申请日：2002-09-25

申请人： Jonathan Ashley ,  William G. Bliss ,  Razmik Karabed ,  Kaichi Zhang

发明人： Jonathan Ashley ,  William G. Bliss ,  Razmik Karabed ,  Kaichi Zhang

IPC分类号： H03M13/00

CPC分类号： H04L1/006 ,  H03M5/145 ,  H03M13/41 ,  H04L1/0041 ,  H04L1/0054

摘要： The present invention relates to a coding system characterized by various combinations of the following properties: 1) Even parity at the output of d of the precoder; 2) A coding rate of 32/34; 3) At least 9 ones per codeword; 4) No more than 13 consecutive zeros in the stream of encoded data (G=13); 5) No more than 13 consecutive zeros in any run of every-other-bit in the stream of codewords (I=13); 6) For closed error events in y or y′ having squared-distance≦(1 to 1.5)×dmfb2 in the detector, the decoder produces at most 4 corresponding erroneous data bytes; 7) Decoding of a 34 bit codeword may begin when 19 of its bits have been received; 8) If the Viterbi detector 108 outputs Non-Return to Zero (NRZ) symbols, then its output is filtered by (1⊕D^2) before being decoded, but if the Viterbi detector outputs NRZ Inverter (NRZI) symbols, then its output is decoded directly; and 9) The even parity is on NRZ symbols.

摘要翻译： 本发明涉及以下特性的各种组合为特征的编码系统：1）预编码器d的输出端的偶校验; 2）编码率32/34; 3）每个码字至少有9个; 4）编码数据流中不超过13个连续的零（G = 13）; 5）代码字流（I = 13）中每个其他位的任何运行中不超过13个连续的零; 6）对于检测器中y或y'具有平方距离<=（1到1.5）xD mfb 2> / 2>的闭合误差事件，解码器产生最多4个相应的 错误的数据字节; 7）当接收到其位的19个时，可以开始对34位码字的解码; 8）如果维特比检测器108输出非归零（NRZ）符号，则在解码之前将其输出滤波为（1⊕D^ 2），但是如果维特比检测器输出NRZ变换器（NRZI）符号，则其 输出直接解码; 和9）偶数奇偶校验位在NRZ符号上。

公开(公告)号：US06819514B1

公开(公告)日：2004-11-16

申请号：US08640351

申请日：1996-04-30

申请人： Richard T. Behrens ,  Li Du ,  William G. Bliss ,  David E. Reed ,  Mark S. Spurbeck

发明人： Richard T. Behrens ,  Li Du ,  William G. Bliss ,  David E. Reed ,  Mark S. Spurbeck

IPC分类号： G11B5035

CPC分类号： G11B20/10194 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/1258 ,  G11B20/1876

摘要： A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.

摘要翻译： 用于磁盘记录的采样幅度读取通道，其异步采样模拟读取信号，根据目标部分响应对所得离散时间采样值进行自适应均衡，通过内插定时恢复提取同步采样值，并从同步采样值检测数字数据 公开了使用维特比序列检测器。 为了最小化来自定时和增益控制环路的干扰，使用最佳正交投影操作将自适应均衡器滤波器的相位和幅度响应约束在预定频率，作为对最小均方（LMS）适配算法的修改。 此外，通过内插定时恢复，均衡器滤波器及其相关等待时间从定时恢复环路中移除，从而允许较高阶离散时间滤波器和较低阶模拟滤波器。

公开(公告)号：US06507546B1

公开(公告)日：2003-01-14

申请号：US09439560

申请日：1999-11-12

申请人： William G. Bliss ,  Sian She ,  Lisa C. Sundell

发明人： William G. Bliss ,  Sian She ,  Lisa C. Sundell

IPC分类号： G11B7005

CPC分类号： G11B20/10287 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/10055

摘要： A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by detecting an estimated data sequence from a sequence of read signal sample values generated by an analog read signal emanating from a read head positioned over the disk storage medium. A sampling device samples the analog read signal to generate the read signal sample values, and a discrete-time equalizer equalizes the read signal sample values according to an asymmetric partial response target comprising a dipulse response of the form: (. . . , 0, 0,+X0,+X1,−X2,−X3,−X4, 0, 0, . . . ) where X0−X4 are non-zero to thereby generate equalized sample values. In the embodiments disclosed herein, X0−X4 are 2,2,1,2,1 respectively. A discrete-time sequence detector detects the estimated data sequence from the equalized sample values.

摘要翻译： 公开了一种采样幅度读取通道，用于通过从由位于盘存储介质上的读取头发出的模拟读取信号产生的读取信号样本值的序列中检测估计的数据序列来读取记录在盘存储介质上的数据。 采样设备对模拟读取信号进行采样以产生读取信号采样值，并且离散时间均衡器根据包括以下形式的二次脉冲响应的不对称部分响应目标来均衡读取信号采样值：其中X0-X4是非 - 从而产生均衡的样本值。 在本文公开的实施方案中，X0-X4分别为2,2,1,2,1。 离散时间序列检测器从均衡的样本值检测估计的数据序列。

公开(公告)号：US06246723B1

公开(公告)日：2001-06-12

申请号：US09072285

申请日：1998-05-04

申请人： William G. Bliss ,  David E. Reed ,  Marvin L. Vis ,  German S. Feyh

发明人： William G. Bliss ,  David E. Reed ,  Marvin L. Vis ,  German S. Feyh

IPC分类号： H04L512

CPC分类号： G11B20/10009 ,  G11B20/10055 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6331 ,  H03M13/6343 ,  H04L1/0054

摘要： A sampled amplitude read channel is disclosed for disc storage systems that extracts early-decisions from a discrete-time trellis sequence detector to generate estimated target values for use in decision-directed timing recovery, gain control, and adaptive equalization. The trellis sequence detector comprises a metric generator for generating error metrics corresponding to a plurality of states of a state transition diagram, and a plurality of path memories which correspond to the paths of a trellis. The path memories store a plurality of survivor sequences which eventually merge into a most likely sequence at the output of the path memories. To reduce the latency in generating the estimated target samples, the trellis sequence detector outputs an early-decision from an intermediate location within the path memories. The early-decision is then converted into the partial response signaling space of the read signal samples. To improve the accuracy in estimating the target sample values, the accumulated metrics of a predetermined number of states are compared and the early-decision value is selected from the path memory having the smallest error metric. Alternatively, a majority-vote circuit evaluates the intermediate values stored in a predetermined number of the path memories and outputs the intermediate value that occurs most frequently. Although the early-decision technique of the present invention requires more latency than a simple slicer circuit, during acquisition the estimated target sample values are not used and therefore the increase in latency is not a significant problem.

摘要翻译： 公开了用于从离散时间网格序列检测器提取早期决定以产生用于决策定时恢复，增益控制和自适应均衡的估计目标值的盘存储系统的采样幅度读取信道。 网格序列检测器包括用于产生与状态转移图的多个状态相对应的误差度量的度量发生器，以及对应于网格的路径的多个路径存储器。 路径存储器存储多个幸存者序列，其最终在路径存储器的输出处合并成最可能的序列。 为了减少生成估计的目标样本的延迟，网格序列检测器从路径存储器内的中间位置输出早期决定。 然后将早期决定转换为读取信号样本的部分响应信令空间。 为了提高估计目标采样值的准确性，比较预定数量状态的累积度量，并从具有最小误差度量的路径存储器中选择早期判定值。 或者，多数投票电路评估存储在预定数量的路径存储器中的中间值，并输出最频繁出现的中间值。 虽然本发明的早期决策技术比简单的限幅器电路需要更多的延迟，但在采集期间，不使用估计的目标采样值，因此等待时间的增加不是一个显着的问题。

公开(公告)号：US6141169A

公开(公告)日：2000-10-31

申请号：US956569

申请日：1997-10-23

申请人： David M. Pietruszynski ,  Jerrell P. Hein ,  William G. Bliss ,  German S. Feyh

发明人： David M. Pietruszynski ,  Jerrell P. Hein ,  William G. Bliss ,  German S. Feyh

IPC分类号： G11B5/00 ,  G11B5/09 ,  G11B7/09 ,  G11B20/10 ,  H03F1/30 ,  H03F3/45 ,  G11B5/02

CPC分类号： H03F3/45748 ,  G11B20/10009 ,  H03F1/303 ,  H03F3/45973 ,  G11B2005/0013 ,  G11B5/09 ,  G11B7/0941 ,  G11B7/0948

摘要： A system and method for an amplifier control circuit is provided which does not require the use of a large off-chip or on-chip capacitor for achieving a low frequency coupling corner, while still effectively allowing AC coupling the data detection circuit. In addition, the input offset voltage to the amplifier may be compensated and the inherent random low frequency input voltages provided to the amplifier may be controlled or canceled. Further, the amplifier control circuitry includes a freeze capability which allows the control circuitry to halt all updates to the input offset/low frequency control circuit when the voltage input signal is interrupted. In addition low frequency control and offset compensation updates may be performed without causing large output signal glitches so that the integrity of the received signal will not be compromised. In a preferred embodiment the system and method may be utilized for data detection circuits utilized in conjunction with optical disks.

摘要翻译： 提供一种用于放大器控制电路的系统和方法，其不需要使用大的片外或片上电容器来实现低频耦合角，同时仍然有效地允许AC耦合数据检测电路。 此外，可以补偿放大器的输入失调电压，并且可以控制或取消提供给放大器的固有的随机低频输入电压。 此外，放大器控制电路包括冻结能力，其允许控制电路在电压输入信号中断时停止对输入偏移/低频控制电路的所有更新。 此外，可以执行低频控制和偏移补偿更新，而不会导致大的输出信号毛刺，从而不会损害接收信号的完整性。 在优选实施例中，系统和方法可以用于与光盘结合使用的数据检测电路。

公开(公告)号：US6023386A

公开(公告)日：2000-02-08

申请号：US961727

申请日：1997-10-31

申请人： David E. Reed ,  William G. Bliss

发明人： David E. Reed ,  William G. Bliss

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B27/30

CPC分类号： G11B20/10055 ,  G11B20/10037 ,  G11B20/1403 ,  G11B27/3027 ,  G11B5/09 ,  G11B20/10009

摘要： In a magnetic disk storage system, a sampled amplitude read channel is disclosed that employs a fault tolerant sync mark detector for detecting a sync mark from the channel samples in order to synchronize a time varying sequence detector. The read channel preferably employs PR4 equalization for timing recovery and gain control, and EEPR4 equalization for sequence detection. The EEPR4 sequence detector operates according to a time varying state machine matched to a predetermined trellis code constraint. Because the state machine is time varying, the data stream must be synchronized at the input of the sequence detector rather than at the output as in the prior art. The present invention provides a fault tolerant sync mark detector that detects a sync mark from the EEPR4 channel samples before being input into the sequence detector. In one embodiment, the sync mark detector accumulates a squared error between the read signal sample values and the target sample values of the target sync mark; the sync mark is detected when the accumulated squared error is less than a predetermined lower threshold. In an alternative embodiment, the sync mark detector computes a correlation between the read signal sample values and the target sample values of the target sync mark; the sync mark is detected when the correlation is greater than a predetermined upper threshold. The correlation sync mark detector is the preferred embodiment because it is insensitive to d.c. offsets, it exhibits excellent performance in detecting short sync marks, and it can be implemented as two cascaded finite impulse response filters without requiring multipliers or squarers.

摘要翻译： 在磁盘存储系统中，公开了一种采样幅度读取通道，其采用容错同步标记检测器来检测来自信道样本的同步标记，以便使时变序列检测器同步。 读通道优选采用PR4均衡来进行定时恢复和增益控制，以及用于序列检测的EEPR4均衡。 EEPR4序列检测器根据与预定网格码约束匹配的时变状态机进行操作。 因为状态机是时变的，所以在现有技术中数据流必须在序列检测器的输入端而不是在输出端被同步。 本发明提供一种容错同步标记检测器，其在输入到序列检测器之前，从EEPR4信道样本中检测同步标记。 在一个实施例中，同步标记检测器在读取信号采样值和目标同步标记的目标采样值之间累积平方误差; 当累积的平方误差小于预定的下限阈值时，检测同步标记。 在替代实施例中，同步标记检测器计算读取信号采样值和目标同步标记的目标采样值之间的相关性; 当相关性大于预定的上限阈值时，检测同步标记。 相关同步标记检测器是优选实施例，因为它对直流不敏感。 它在检测短同步标记方面具有出色的性能，并且可以实现为两个级联有限脉冲响应滤波器，而不需要乘法器或平方器。

公开(公告)号：US5771127A

公开(公告)日：1998-06-23

申请号：US681678

申请日：1996-07-29

申请人： David E. Reed ,  William R. Foland, Jr. ,  William G. Bliss ,  Richard T. Behrens ,  Lisa C. Sundell

发明人： David E. Reed ,  William R. Foland, Jr. ,  William G. Bliss ,  Richard T. Behrens ,  Lisa C. Sundell

IPC分类号： G11B20/10 ,  G11B20/14 ,  G11B5/09

CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/1426

摘要： In a computer disk storage system for recording binary data, a sampled amplitude read channel comprises a sampling device for asynchronously sampling pulses in an analog read signal from a read head positioned over a disk storage medium, interpolated timing recovery for generating synchronous sample values, and a sequence detector for detecting the binary data from the synchronous sample values. The sequence detector comprises a demodulator for detecting a preliminary binary sequence which may contain bit errors, a remodulator for remodulating to estimated sample values, a means for generating sample error values, an error pattern detector for detecting the bit errors, an error detection validator, and an error corrector for correcting the bit errors. The remodulator comprises a partial erasure circuit which compensates for the non-linear reduction in amplitude of a primary pulse caused by secondary pulses located near the primary pulse. The error pattern detector comprises a peak error pattern detector and, if an error pattern is detected, a means for disabling the error pattern detector until the detected error pattern has been fully processed. The error detection validator checks the validity of a detected error event and, if valid, enables operation of the error corrector.

摘要翻译： 在用于记录二进制数据的计算机磁盘存储系统中，采样幅度读取通道包括用于从位于盘存储介质上的读取头的模拟读取信号中异步采样脉冲的采样装置，用于产生同步采样值的内插定时恢复，以及 序列检测器，用于从同步样本值检测二进制数据。 序列检测器包括用于检测可能包含位错误的初步二进制序列的解调器，用于重新调制到估计样本值的再调制器，用于产生采样误差值的装置，用于检测位错误的误差模式检测器，错误检测验证器， 以及用于校正位错误的纠错器。 再调制器包括部分擦除电路，其补偿由位于主脉冲附近的次级脉冲引起的初级脉冲的幅度的非线性减小。 误差模式检测器包括峰值误差模式检测器，并且如果检测到错误模式，则用于禁止错误模式检测器的装置，直到检测到的错误模式被完全处理为止。 错误检测验证器检查检测到的错误事件的有效性，如果有效，则允许错误校正器的操作。