-
公开(公告)号：US5761137A
公开(公告)日：1998-06-02
申请号：US782561
申请日：1997-01-09
IPC分类号： G06F12/02 , G11C7/10 , G11C11/401 , G11C7/00
CPC分类号： G11C7/1033 , G11C7/1072
摘要： A data latching mechanism uses Column Address Strobe (CAS) signals to effect one-cycle DRAM page-mode access at high operation frequency.
摘要翻译： 数据锁存机制使用列地址选通（CAS）信号在高工作频率下实现一周期DRAM页模式存取。
-
公开(公告)号：US11040782B1
公开(公告)日：2021-06-22
申请号：US16359147
申请日：2019-03-20
摘要： A portable platform device is described comprising a central body and a plurality of legs located on the central body near a distal end of the central body and spaced radially around the central body wherein the legs are configured for placement on a surface. A ball joint is mounted at its distil end to a proximal end of the central body and a platform is configured to be fixed to a proximal end of the ball joint and configured to be adjustable to a horizontally level and vertically plumb position.
-
公开(公告)号：USD594054S1
公开(公告)日：2009-06-09
申请号：US29320684
申请日：2008-07-01
-
公开(公告)号：US20130046934A1
公开(公告)日：2013-02-21
申请号：US13209439
申请日：2011-08-15
IPC分类号： G06F12/08
CPC分类号： G06F12/0897
摘要： A caching circuit includes tag memories for storing tagged addresses of a first cache. On-chip data memories are arranged in the same die as the tag memories, and the on-chip data memories form a first sub-hierarchy of the first cache. Off-chip data memories are arranged in a different die as the tag memories, and the off-chip data memories form a second sub-hierarchy of the first cache. Sources (such as processors) are arranged to use the tag memories to service first cache requests using the first and second sub-hierarchies of the first cache.
摘要翻译： 缓存电路包括用于存储第一高速缓存的标记地址的标签存储器。 片上数据存储器被布置在与标签存储器相同的芯片中，并且片上数据存储器形成第一高速缓存的第一子层。 片外数据存储器被布置在不同的管芯中作为标签存储器，并且片外数据存储器形成第一高速缓存的第二子层级。 源（例如处理器）被布置为使用标签存储器来使用第一高速缓存的第一和第二子层次来服务第一高速缓存请求。
-
-
-
搜索结果
4 条记录 (耗时 0.043 秒)
