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1.发明授权Self timed register file having bit storage cells with emitter-coupled output selectors for common bits sharing a common pull-up resistor and a common current sink 失效自定时寄存器文件，具有用于通用位的发射耦合输出选择器的位存储单元共享普通上拉电阻和常用电流信号
公开(公告)号：US5107462A
公开(公告)日：1992-04-21
申请号：US306445
申请日：1989-02-03
CPC分类号： G06F5/06
摘要： A self time register (STREG) 44 is constructed on a single custom ECL integrated circuit and has provisions for generating its own internal clock signal. The STREG 44 includes a set of latches 80a-80q for temporarily storing the data delivered thereto concurrent with the system clock pulse. Thereafter, the internally generated clock pulse (W.sub.PULS) controls the write operation of the temporary latches into the STREG 44. The STREG has data storage registers including bit storage cells which receive the data in response to the internally generated clock pulse. To selectively output the data, the bit storage cells have emitter-coupled output selectors, and the output selectors for common bits share a common current sink and a common pull-up resistor at which a single-bit output signal is provided from a selected register. Preferably, each bit storage cell has a first output selector for a first data output port, and a second output selector for a second data output port. By sharing of a common pull-up resistor and a current sink for each bit position of each output port, an economy of components can be realized.
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2.发明授权Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers 失效基于检测指定器寄存器的修改值，同时或顺序地解码可变长度管道指令的多个指定符
公开(公告)号：US5167026A
公开(公告)日：1992-11-24
申请号：US306833
申请日：1989-02-03
CPC分类号： G06F9/30167 , G06F9/30149 , G06F9/30163 , G06F9/30178 , G06F9/3816 , G06F9/3822 , G06F9/3824 , G06F9/3863
摘要： In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the excellent unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction. Preferably, the proper initial value is obtained prior to the incrementing or decrementing of the conflicting register by putting the instruction decoder into a special IRC mode in which only one specifier is decoded per cycle, and if a specifier being decoded is a register specifier, the content of the specified register is transmitted to the execution unit. Circuitry for detecting an intra-instruction read conflict is disclosed as well as an efficient method for handling interrupts, exceptions and flushes that may occur during the processing of an instruction having an intra-instruction read conflict.
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