公开(公告)号：US20120272196A1

公开(公告)日：2012-10-25

申请号：US13541638

申请日：2012-07-03

申请人： William S. Wong ,  Fei Liu ,  Been-Der Chen ,  Yen-Wen Lu

发明人： William S. Wong ,  Fei Liu ,  Been-Der Chen ,  Yen-Wen Lu

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix.

摘要翻译： 用于近程校正的多变量求解器使用雅可比矩阵近似设计循环的连续迭代中的段位置的扰动效应。 该问题被形成为具有框，线性等式和线性不等式约束的约束最小化问题。 为了提高计算效率，忽略非局部相互作用，这导致了稀疏的雅可比矩阵。

公开(公告)号：US08560979B2

公开(公告)日：2013-10-15

申请号：US13541638

申请日：2012-07-03

申请人： William S. Wong ,  Fei Liu ,  Been-Der Chen ,  Yen-Wen Lu

发明人： William S. Wong ,  Fei Liu ,  Been-Der Chen ,  Yen-Wen Lu

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix.

摘要翻译： 用于近程校正的多变量求解器使用雅可比矩阵近似设计循环的连续迭代中的段位置的扰动效应。 该问题被形成为具有框，线性等式和线性不等式约束的约束最小化问题。 为了提高计算效率，忽略非局部相互作用，这导致了稀疏的雅可比矩阵。

公开(公告)号：US20100167184A1

公开(公告)日：2010-07-01

申请号：US12644790

申请日：2009-12-22

申请人： William S. Wong ,  Fei Liu ,  Been-Der Chen ,  Yen Wen Lu

发明人： William S. Wong ,  Fei Liu ,  Been-Der Chen ,  Yen Wen Lu

IPC分类号： G03F1/00 ,  G06F17/50

CPC分类号： G03F1/36

摘要： A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix.

摘要翻译： 用于近程校正的多变量求解器使用雅可比矩阵近似设计循环的连续迭代中的段位置的扰动效应。 该问题被形成为具有框，线性等式和线性不等式约束的约束最小化问题。 为了提高计算效率，忽略非局部相互作用，这导致了稀疏的雅可比矩阵。

公开(公告)号：US08239786B2

公开(公告)日：2012-08-07

申请号：US12644790

申请日：2009-12-22

申请人： William S. Wong ,  Fei Liu ,  Been-Der Chen ,  Yen-Wen Lu

发明人： William S. Wong ,  Fei Liu ,  Been-Der Chen ,  Yen-Wen Lu

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix.

摘要翻译： 用于近程校正的多变量求解器使用雅可比矩阵近似设计循环的连续迭代中的段位置的扰动效应。 该问题被形成为具有框，线性等式和线性不等式约束的约束最小化问题。 为了提高计算效率，忽略非局部相互作用，这导致了稀疏的雅可比矩阵。

公开(公告)号：US07707538B2

公开(公告)日：2010-04-27

申请号：US11764128

申请日：2007-06-15

申请人： William S. Wong ,  Been-Der Chen ,  Yenwen Lu ,  Jiangwei Li ,  Tatsuo Nishibe

发明人： William S. Wong ,  Been-Der Chen ,  Yenwen Lu ,  Jiangwei Li ,  Tatsuo Nishibe

IPC分类号： G06F17/50

CPC分类号： G03F1/144 ,  G03F1/36 ,  G03F7/70441 ,  G03F7/705

摘要： The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout.

摘要翻译： 本发明的方法跟踪掩模布局中边缘段的集体移动如何在布局中的控制点处改变抗蚀剂图像值，同时确定布局中每个边缘段的校正量。 用于表示掩模布局中每个边缘段的移动的集合效果的多分离器矩阵用于同时确定掩模布局中每个边缘段的校正量。

公开(公告)号：US20100161093A1

公开(公告)日：2010-06-24

申请号：US12721331

申请日：2010-03-10

申请人： William S. Wong ,  Been-Der Chen ,  Yenwen Lu ,  Jiangwei Li ,  Tatsuo Nishibe

发明人： William S. Wong ,  Been-Der Chen ,  Yenwen Lu ,  Jiangwei Li ,  Tatsuo Nishibe

IPC分类号： G06F17/50

CPC分类号： G03F1/144 ,  G03F1/36 ,  G03F7/70441 ,  G03F7/705

摘要： The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout.

摘要翻译： 本发明的方法跟踪掩模布局中边缘段的集体移动如何在布局中的控制点处改变抗蚀剂图像值，同时确定布局中每个边缘段的校正量。 用于表示掩模布局中每个边缘段的移动的集合效果的多分离器矩阵用于同时确定掩模布局中每个边缘段的校正量。

公开(公告)号：US08291352B2

公开(公告)日：2012-10-16

申请号：US12721331

申请日：2010-03-10

申请人： William S. Wong ,  Been-Der Chen ,  Yenwen Lu ,  Jiangwei Li ,  Tatsuo Nishibe

发明人： William S. Wong ,  Been-Der Chen ,  Yenwen Lu ,  Jiangwei Li ,  Tatsuo Nishibe

IPC分类号： G06F17/50

CPC分类号： G03F1/144 ,  G03F1/36 ,  G03F7/70441 ,  G03F7/705

摘要： The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout.

摘要翻译： 本发明的方法跟踪掩模布局中边缘段的集体移动如何在布局中的控制点处改变抗蚀剂图像值，同时确定布局中每个边缘段的校正量。 用于表示掩模布局中每个边缘段的移动的集合效果的多分离器矩阵用于同时确定掩模布局中每个边缘段的校正量。

公开(公告)号：US10066829B2

公开(公告)日：2018-09-04

申请号：US15139648

申请日：2016-04-27

申请人： William S. Wong ,  John S. Morreale

发明人： William S. Wong ,  John S. Morreale

IPC分类号： F21V33/00 ,  H05K1/03 ,  H05K1/18 ,  F21Y115/10 ,  F21Y107/70 ,  H05K1/11 ,  A41D27/08 ,  A41D1/00

摘要： An electronic fabric can include a first fabric layer, a second fabric layer, and a plurality of electronic devices. The first fabric layer can include a first set of conductive wires extending longitudinally in a first direction. The second fabric layer can define a plurality of apertures, can include a second set of conductive wires extending longitudinally in a second direction, and can be coupled to the first fabric layer such that each of the first set of conductive wires is arranged at a location of one of the plurality of apertures. Each electronic device can have a first terminal electrically coupled with one of the first set of conductive wires and a second terminal electrically coupled to one of the second set of conductive wires. The first terminal can be electrically coupled with the one of the first set of conductive wires through one of the plurality of apertures.

公开(公告)号：US08492876B2

公开(公告)日：2013-07-23

申请号：US12253390

申请日：2008-10-17

申请人： William S. Wong ,  Brent S. Krusor ,  Robert A. Street

发明人： William S. Wong ,  Brent S. Krusor ,  Robert A. Street

IPC分类号： H01L29/06

CPC分类号： H05K3/0044 ,  G02F2201/56 ,  H01L27/14603 ,  H01L27/14692 ,  H01L27/14812 ,  H01L29/78603

摘要： A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure. A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being arranged to as to increase a radius of curvature to meet a stress relief parameter when the substrate is shaped, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure. A three-dimensional electronic device having an electronic device formed on a flexible substrate, the flexible substrate formed into a three-dimensional structure, wedged-shaped portions removed from the substrate to allow the substrate to be formed into the three-dimensional structure, and a stress relief feature arranged adjacent to the wedge-shaped portions.

摘要翻译： 形成三维电子器件的方法包括在二维柔性基板上形成至少一个电子器件，该电子器件根据三维结构形成，切割二维柔性基片，切割 被设置成允许二维基底成形，切口具有至少一个应力消除特征，并且成形二维柔性基底以形成三维结构，应力消除特征被设置为减轻二维基底中的应力 三维结构。 形成三维电子器件的方法包括在二维柔性基板上形成至少一个电子器件，该电子器件根据三维结构形成，切割二维柔性基片，切割 被布置成当基底成形时增加曲率半径以满足应力消除参数，并且将二维柔性基底成形以形成三维结构。 一种具有形成在柔性基板上的电子器件的三维电子器件，形成为三维结构的柔性衬底，从衬底移除楔形部分以使衬底形成三维结构;以及 紧邻楔形部分布置的应力消除特征。

公开(公告)号：US08411075B2

公开(公告)日：2013-04-02

申请号：US12206690

申请日：2008-09-08

申请人： Sanjiv Sambandan ,  William S. Wong ,  Robert A. Street

发明人： Sanjiv Sambandan ,  William S. Wong ,  Robert A. Street

IPC分类号： G06F3/038 ,  G06G5/00

CPC分类号： G06F3/038

摘要： A pixel circuit including a first transistor; a second transistor, the first transistor and the second transistor serially coupled between a first power supply terminal and a second power supply terminal; and a first capacitor coupled between a gate of the first transistor and a gate of the second transistor, and an electronic sheet including the same.

摘要翻译： 一种像素电路，包括第一晶体管; 第二晶体管，第一晶体管和第二晶体管，串联耦合在第一电源端子和第二电源端子之间; 以及耦合在所述第一晶体管的栅极和所述第二晶体管的栅极之间的第一电容器以及包括所述第一晶体管的电子薄片。