公开(公告)号：US20190187551A1

公开(公告)日：2019-06-20

申请号：US16327716

申请日：2017-08-02

申请人： HOYA CORPORATION

发明人： Hiroyuki IWASHITA ,  Atsushi MATSUMOTO ,  Osamu NOZAWA

IPC分类号： G03F1/32 ,  G03F1/58 ,  H01L21/3065 ,  G03F1/00 ,  G03F1/80

CPC分类号： G03F1/32 ,  G03F1/144 ,  G03F1/26 ,  G03F1/58 ,  G03F1/80 ,  H01L21/3065

摘要： Provided is a mask blank including a phase shift film having a transmittance of 20% or more difficult to achieve in a phase shift film of a single layer made of a silicon nitride material, and the phase shift film is achieved by using a structure having two or more sets of a stacked structure, each set including a low transmission layer and a high transmission layer disposed in order from a transparent substrate side.The mask blank includes a phase shift film on a transparent substrate. The phase shift film has a function of transmitting exposure light of an ArF excimer laser at a transmittance of 20% or more. The mask blank has two or more sets of a stacked structure, each set including a low transmission layer and a high transmission layer. The low transmission layer is formed of a silicon nitride-based material. The high transmission layer is formed of a silicon oxide-based material. The high transmission layer provided at an uppermost position is thicker than the high transmission layer provided at a position other than the uppermost position. The low transmission layer is thicker than the high transmission layer provided at a position other than the uppermost position.

公开(公告)号：US20180239861A1

公开(公告)日：2018-08-23

申请号：US15959123

申请日：2018-04-20

申请人： ASML NETHERLANDS B.V.

发明人： Luoqi Chen ,  Jun Ye ,  Yu Cao

IPC分类号： G06F17/50 ,  G03F7/20 ,  G03F1/00 ,  G03F1/36

CPC分类号： G06F17/5081 ,  G03F1/144 ,  G03F1/36 ,  G03F7/70083 ,  G03F7/70125 ,  G03F7/70441 ,  G03F7/705 ,  G06F17/5068

摘要： The present disclosure relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present disclosure significantly speeds up the convergence of the optimization by allowing direct computation of gradient of the cost function. According to other aspects, the present disclosure allows for simultaneous optimization of both source and mask, thereby significantly speeding the overall convergence. According to still further aspects, the present disclosure allows for free-form optimization, without the constraints required by conventional optimization techniques.

公开(公告)号：US10018907B2

公开(公告)日：2018-07-10

申请号：US15041149

申请日：2016-02-11

申请人： Carl Zeiss SMT GmbH

发明人： Boris Bittner ,  Norbert Wabra ,  Sonja Schneider ,  Ricarda Schoemer ,  Martin von Hodenberg

IPC分类号： G06F17/50 ,  G03F1/70 ,  G03F7/20 ,  G03F1/00

CPC分类号： G03F1/70 ,  G03F1/144 ,  G03F7/70258 ,  G03F7/705 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12

摘要： A method of operating a microlithographic projection exposure apparatus includes, in a first step, providing a projection objective that includes a plurality of real manipulators. In a second step, a virtual manipulator is defined that is configured to produce preliminary control signals for at least two of the real manipulators. In a third step, performed during operation of the apparatus, a real image error of the projection objective is determined. In a fourth step, a desired corrective effect is determined. In a fifth step, first virtual control signals for the virtual manipulator are determined. In a sixth step, second virtual control signals for the real manipulators are determined.

公开(公告)号：US09953127B2

公开(公告)日：2018-04-24

申请号：US14822661

申请日：2015-08-10

申请人： ASML NETHERLANDS B.V.

发明人： Luoqi Chen ,  Jun Ye ,  Yu Cao

IPC分类号： G06F17/50 ,  G03F7/20 ,  G03F1/00 ,  G03F1/36

CPC分类号： G06F17/5081 ,  G03F1/144 ,  G03F1/36 ,  G03F7/70083 ,  G03F7/70125 ,  G03F7/70441 ,  G03F7/705 ,  G06F17/5068

摘要： The present disclosure relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present disclosure significantly speeds up the convergence of the optimization by allowing direct computation of gradient of the cost function. According to other aspects, the present disclosure allows for simultaneous optimization of both source and mask, thereby significantly speeding the overall convergence. According to still further aspects, the present disclosure allows for free-form optimization, without the constraints required by conventional optimization techniques.

公开(公告)号：US09947765B2

公开(公告)日：2018-04-17

申请号：US15351657

申请日：2016-11-15

申请人： Texas Instruments Incorporated

发明人： Younsung Choi ,  Shashank Ekbote ,  Gregory Charles Baldwin

IPC分类号： H01L29/66 ,  H01L27/02 ,  H01L21/28 ,  H01L21/027 ,  G03F1/00 ,  G06F17/50

CPC分类号： H01L29/66545 ,  G03F1/144 ,  G06F17/5072 ,  G06F2217/72 ,  H01L21/0271 ,  H01L21/28123 ,  H01L27/0207

摘要： A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit.

公开(公告)号：US09934350B2

公开(公告)日：2018-04-03

申请号：US14874134

申请日：2015-10-02

申请人： ASML NETHERLANDS B.V.

发明人： Hua-Yu Liu

IPC分类号： G06F17/50 ,  G03F1/00 ,  G03F1/36 ,  G03F7/20

CPC分类号： G06F17/5081 ,  G03F1/144 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70425 ,  G03F7/70441 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/50 ,  G06F17/5009

摘要： The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

公开(公告)号：US20170322486A1

公开(公告)日：2017-11-09

申请号：US15658721

申请日：2017-07-25

申请人： GLOBALFOUNDRIES INC.

发明人： Ayman Hamouda

IPC分类号： G03F1/36 ,  G06F17/50 ,  G03F1/00

CPC分类号： G03F1/36 ,  G03F1/144 ,  G06F17/5068 ,  G06F17/5081

摘要： Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.

公开(公告)号：US09779186B2

公开(公告)日：2017-10-03

申请号：US14282754

申请日：2014-05-20

申请人： ASML NETHERLANDS B.V.

发明人： Jun Ye ,  Yu Cao ,  Hanying Feng

IPC分类号： G06F17/50 ,  G03F1/00 ,  G03F1/36

CPC分类号： G06F17/5009 ,  G03F1/144 ,  G03F1/36

摘要： Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window. In one embodiment, the SRAF guidance map is used to determine SRAF placement rules and/or to fine-tune already-placed SRAFs. The SRAF guidance map can be used directly to place SRAFs in a mask layout. Mask layout data including SRAFs may be generated, wherein the SRAFs are placed according to the SRAF guidance map. The SRAF guidance map can comprise an image in which each pixel value indicates whether the pixel would contribute positively to edge behavior of features in the mask layout if the pixel is included as part of a sub-resolution assist feature.

公开(公告)号：US09761436B2

公开(公告)日：2017-09-12

申请号：US14334904

申请日：2014-07-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Ming-Feng Shieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC分类号： H01L21/027 ,  H01L21/02 ,  H01L21/308 ,  G03F7/20 ,  G03F1/00 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/302 ,  H01L21/033

CPC分类号： H01L21/02071 ,  G03F1/144 ,  G03F7/70466 ,  H01L21/0337 ,  H01L21/302 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

公开(公告)号：US20170124243A1

公开(公告)日：2017-05-04

申请号：US15357716

申请日：2016-11-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Ming Chang ,  Kuei-Liang Lu

IPC分类号： G06F17/50 ,  H01L27/02

CPC分类号： G06F17/5072 ,  G03F1/144 ,  G03F1/70 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/06 ,  H01L21/027 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes first and second features, each including an end portion arranged along a common axis, and separated by a space. The end portion of the first feature includes a first indention adjacent to the space. The end portion of the second feature includes a first indention adjacent to the space, mirroring the first indention of the first feature about the space. The end portions are substantially similar in shape.