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1.发明授权Border-enhanced sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture 有权边界增强滑动窗口方案（SWS），用于确定基于网格的时钟架构中的时钟时序公开(公告)号：US07788613B2
公开(公告)日：2010-08-31
申请号：US11428995
申请日：2006-07-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh, determining multiple original window locations covering the clock mesh. Each window location includes one or more of the sequential elements on the chip. The method also includes, for each original window location, expanding the original window location in one or more directions to generate a larger window location and generating a mesh simulation model including a detailed model inside the larger window location and an approximate model outside the larger window location, simulating the mesh simulation model, and measuring clock timing for the sequential elements in the window location based on the mesh simulation model. The method also includes collecting timing information on the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.
摘要翻译： 在一个实施例中，一种方法包括访问包括多个顺序元素和时钟网格的芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的一组参数。 该方法还包括使用芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的参数集合，确定覆盖时钟网格的多个原始窗口位置。 每个窗口位置包括芯片上的一个或多个顺序元件。 该方法还包括对于每个原始窗口位置，在一个或多个方向上扩展原始窗口位置以生成更大的窗口位置并生成包括较大窗口位置内的详细模型的网格模拟模型以及较大窗口外的近似模型 位置，模拟网格模拟模型，并基于网格模拟模型测量窗口位置中的顺序元素的时钟时序。 该方法还包括基于原始窗口位置中的顺序元素的测量时钟定时来收集关于芯片上的顺序元件的定时信息。
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公开(公告)号：US20100049481A1
公开(公告)日：2010-02-25
申请号：US12197572
申请日：2008-08-25
IPC分类号： G06F17/10
CPC分类号： G06F1/10 , G06F17/5036 , G06F2217/62
摘要： A system and method for constructing a clock tree based on replica stages is described. The system and method may comprise determining a size of an input buffer for driving a load capacitance of the output buffer based on a fanout, determining a wire width and a wire length based on the size of the output buffer, the fanout and a replica stage mathematical model, and connecting the output buffer and the corresponding input buffer to a conductor routed on one or more predetermined metal layers and having the wire length and the wire width. The conductor is placed within ground shields having a fixed width.
摘要翻译： 描述了一种基于副本级构建时钟树的系统和方法。 系统和方法可以包括基于扇出来确定用于驱动输出缓冲器的负载电容的输入缓冲器的大小，基于输出缓冲器的大小，扇出和复制级确定线宽度和线长度 数学模型，以及将输出缓冲器和相应的输入缓冲器连接到在一个或多个预定金属层上布线并具有线长度和线宽度的导体。 导体放置在具有固定宽度的接地屏蔽内。
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3.发明申请System and Method for Providing an Improved Sliding Window Scheme for Clock Mesh Analysis 有权用于提供时钟网格分析的改进的滑动窗口方案的系统和方法公开(公告)号：US20070283305A1
公开(公告)日：2007-12-06
申请号：US11754586
申请日：2007-05-29
申请人： Subodh M. Reddy , Rajeev Murgai
发明人： Subodh M. Reddy , Rajeev Murgai
CPC分类号： G06F17/5031 , G06F1/10 , G06F2217/62
摘要： A method is provided and includes accessing a description of a chip, which includes sequential elements and a clock mesh. Items used include: the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh. Additionally, the method includes determining a plurality of original window locations covering the clock mesh. Further, for each original window location, the method includes expanding the original window location in one or more directions to generate a larger window location; generating a mesh simulation model inside the larger window location; simulating the mesh simulation model; measuring clock timing for the sequential elements in the original window location based on the simulation of the mesh simulation model; and collecting timing information on all the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.
摘要翻译： 提供了一种方法，包括访问包括顺序元素和时钟网格的芯片的描述。 使用的项目包括：芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的参数集。 另外，该方法包括确定覆盖时钟网格的多个原始窗口位置。 此外，对于每个原始窗口位置，该方法包括在一个或多个方向上扩展原始窗口位置以生成较大的窗口位置; 在较大的窗口位置内生成网格模拟模型; 模拟网格模拟模型; 基于网格模拟模型的模拟测量原始窗口位置中的顺序元素的时钟定时; 并且基于原始窗口位置中的顺序元素的测量时钟定时来收集芯片上所有顺序元件的定时信息。
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4.发明授权System and method for providing an improved sliding window scheme for clock mesh analysis 有权为时钟网格分析提供改进的滑动窗口方案的系统和方法公开(公告)号：US07802215B2
公开(公告)日：2010-09-21
申请号：US11754586
申请日：2007-05-29
申请人： Subodh M. Reddy , Rajeev Murgai
发明人： Subodh M. Reddy , Rajeev Murgai
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F1/10 , G06F2217/62
摘要： A method is provided and includes accessing a description of a chip, which includes sequential elements and a clock mesh. Items used include: the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh. Additionally, the method includes determining a plurality of original window locations covering the clock mesh. Further, for each original window location, the method includes expanding the original window location in one or more directions to generate a larger window location; generating a mesh simulation model inside the larger window location; simulating the mesh simulation model; measuring clock timing for the sequential elements in the original window location based on the simulation of the mesh simulation model; and collecting timing information on all the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.
摘要翻译： 提供了一种方法，包括访问包括顺序元素和时钟网格的芯片的描述。 使用的项目包括：芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的参数集。 另外，该方法包括确定覆盖时钟网格的多个原始窗口位置。 此外，对于每个原始窗口位置，该方法包括在一个或多个方向上扩展原始窗口位置以生成较大的窗口位置; 在较大的窗口位置内生成网格模拟模型; 模拟网格模拟模型; 基于网格仿真模型的模拟测量原始窗口位置中的顺序元素的时钟定时; 并且基于原始窗口位置中的顺序元素的测量时钟定时来收集芯片上所有顺序元件的定时信息。
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公开(公告)号：US07246335B2
公开(公告)日：2007-07-17
申请号：US11058900
申请日：2005-02-15
CPC分类号： G06F17/5036
摘要： In one embodiment, a method for analyzing substrate noise includes applying a static timing analysis (STA) algorithm to a description of a digital circuit. Application of the STA algorithm generates timing information on one or more gates in the digital circuit. The method also includes applying a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit. Application of the CWG algorithm generates a current waveform. The method also includes generating a reduced model (RM) of the digital circuit for simulation according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit. Simulation of the RM of the digital circuit generates an indication of noise in a substrate associated with the digital circuit.
摘要翻译： 在一个实施例中，用于分析衬底噪声的方法包括将静态时序分析（STA）算法应用于数字电路的描述。 STA算法的应用在数字电路中的一个或多个门上产生定时信息。 该方法还包括将电流波形生成（CWG）算法应用于数字电路的描述，数字电路中的一个或多个门上的定时信息以及数字电路中的开关活动的描述。 CWG算法的应用产生电流波形。 该方法还包括根据数字电路的描述，电流波形和与数字电路相关联的封装的模型，生成用于模拟的数字电路的简化模型（RM）。 数字电路的RM的仿真产生与数字电路相关联的衬底中的噪声的指示。
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公开(公告)号：US07801718B2
公开(公告)日：2010-09-21
申请号：US11680020
申请日：2007-02-28
申请人： Subodh M. Reddy , Gustavo R. Wilke , Rajeev Murgai
发明人： Subodh M. Reddy , Gustavo R. Wilke , Rajeev Murgai
CPC分类号： G06F17/5036
摘要： A method of analyzing timing uncertainty involves creating an accurate model of one or more circuit elements of a mesh circuit residing within a window that covers a subset of the mesh circuit. An approximate model of one or more circuit elements of the mesh circuit residing outside of the window is also created. Monte Carlo simulations are performed on the combination of the accurate model and the approximate model to determine a plurality of timing values, wherein each run of the Monte Carlo simulation varies one or more parameters potentially affecting the operation of the mesh circuit. An uncertainty associated with the circuit elements is determined, based at least in part on the plurality of timing values. One embodiment considers clock as the signal whose timing uncertainty can be determined. Other embodiments model and simulate the global drive circuit that drives the mesh circuit separately from the mesh circuit to take into account common path correlations in the drive circuit.
摘要翻译： 分析定时不确定性的方法涉及创建驻留在覆盖网状电路的子集的窗口内的网状电路的一个或多个电路元件的精确模型。 还创建了位于窗户外部的网状电路的一个或多个电路元件的近似模型。 对精确模型和近似模型的组合执行蒙特卡罗模拟，以确定多个时间值，其中蒙特卡洛模拟的每次运行改变潜在地影响网格电路的操作的一个或多个参数。 至少部分地基于多个定时值来确定与电路元件相关联的不确定性。 一个实施例将时钟视为可以确定其定时不确定性的信号。 其他实施例模拟和模拟驱动网格电路与网状电路分离的全局驱动电路，以考虑驱动电路中的公共路径相关性。
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7.发明授权Computing current in a digital circuit based on an accurate current model for library cells 失效基于图书馆细胞的精确电流模型，在数字电路中计算电流公开(公告)号：US07313771B2
公开(公告)日：2007-12-25
申请号：US11096138
申请日：2005-03-31
申请人： Subodh M. Reddy , Rajeev Murgai
发明人： Subodh M. Reddy , Rajeev Murgai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment, a method for computing current in a digital circuit based on an accurate current model for library cells includes accessing a cell library, for each cell in the cell library corresponding to a cell in a digital circuit, generating multiple waveforms of current drawn by the cell from a power supply according to one or more predetermined values of one or more input parameters of the cell, analyzing the digital circuit to determine one or more actual values of the input parameters of each cell in the digital circuit, for each of the cells in the digital circuit, generating a current waveform according to the determined actual values of the input parameters and a waveform of current drawn by the cell from the power supply generated by the characterization module corresponding to the determined actual values of the input parameters, and summing the current waveforms of the cells in the digital circuit to generate a waveform of current drawn by the digital circuit from the power supply for use in a pattern-dependent methodology (PDM) or a patten-independent methodology (PIM).
摘要翻译： 在一个实施例中，一种用于基于用于库单元的精确当前模型来计算数字电路中的电流的方法包括：对与数字电路中的单元相对应的单元库中的每个单元访问单元库，生成电流绘制的多个波形 根据单元的一个或多个输入参数的一个或多个预定值从电源供电，分析数字电路以确定数字电路中每个单元的输入参数的一个或多个实际值， 数字电路中的单元，根据所确定的输入参数的实际值产生电流波形，并根据所确定的输入参数的实际值，由表征模块生成的电源产生的电池的电流波形， 并且对数字电路中的单元的电流波形求和，以产生由数字电路从该数字电路中抽出的电流波形 用于依赖于模式的方法（PDM）或独立于图样的方法（PIM）的电源。
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8.发明授权Sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture 有权用于确定基于网格的时钟架构中的时钟定时的滑动窗口方案（SWS）公开(公告)号：US07725852B2
公开(公告)日：2010-05-25
申请号：US11428986
申请日：2006-07-06
申请人： Hongyu Chen , William W. Walker , Rajeev Murgai
发明人： Hongyu Chen , William W. Walker , Rajeev Murgai
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/62
摘要： In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh, determining multiple window locations covering the clock mesh. Each window location includes one or more of the sequential elements on the chip. The method also includes, for each window location, generating a mesh simulation model including a detailed model inside the window location and an approximate model outside the window location, simulating the mesh simulation model, and measuring clock timing for the sequential elements in the window location based on the mesh simulation model. The method also includes collecting timing information on the sequential elements on the chip based on the measured clock timing for the sequential elements in the window locations.
摘要翻译： 在一个实施例中，一种方法包括访问包括多个顺序元素和时钟网格的芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的一组参数。 该方法还包括使用芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的参数集，确定覆盖时钟网格的多个窗口位置。 每个窗口位置包括芯片上的一个或多个顺序元件。 该方法还包括对于每个窗口位置，生成包括窗口位置内的详细模型和窗口位置外的近似模型的网格模拟模型，模拟网格模拟模型，以及测量窗口位置中的顺序元素的时钟定时 基于网格模拟模型。 该方法还包括基于窗口位置中的顺序元素的测量时钟定时来收集关于芯片上的顺序元件的定时信息。
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9.发明授权Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree 有权估计电路的时钟树中的抖动，并合成抖动感知和偏斜感知时钟树公开(公告)号：US07890904B2
公开(公告)日：2011-02-15
申请号：US11421988
申请日：2006-06-02
申请人： Rajeev Murgai , William W. Walker
发明人： Rajeev Murgai , William W. Walker
CPC分类号： G06F1/10 , G06F17/5045
摘要： In one embodiment, a method for computing jitter in a clock tree includes dividing a clock tree into a plurality of stages and computing jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree. The model includes a representation of each source of jitter in the circuit. The method also includes, to compute jitter associated with a path or a pair of paths in the clock tree, statistically combining the jitter in each of the stages of the path or the pair of paths in the clock tree with each other.In one embodiment, to efficiently compute jitter and to achieve zero clock skew, a method synthesizes a symmetrical clock tree of a circuit in which corresponding stages in all paths from a root of the clock tree to sinks of the clock tree exhibit approximate electrical equivalence to each other.
摘要翻译： 在一个实施例中，一种用于计算时钟树中的抖动的方法包括：将时钟树划分成多个级，并且根据与时钟树相关联的电路的至少一部分的模型计算一个或多个级中的抖动 。 该模型包括电路中每个抖动源的表示。 该方法还包括：计算与时钟树中的路径或一对路径相关联的抖动，将时钟树中的路径或路径对中的每个阶段中的抖动统一组合。 在一个实施例中，为了有效地计算抖动并实现零时钟偏移，一种方法合成电路的对称时钟树，其中从时钟树的根到时钟树的汇的所有路径中的相应阶段呈现近似的电等效 彼此。
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公开(公告)号：US20060129960A1
公开(公告)日：2006-06-15
申请号：US11210182
申请日：2005-08-22
申请人： Rajeev Murgai
发明人： Rajeev Murgai
CPC分类号： G06F17/5068
摘要： In one embodiment, a method for layout-driven, area-constrained design optimization includes accessing a design and a layout of the design. The design includes one or more gates and one or more nets coupling the gates to each other. The layout includes blocks that partition a chip area of the design. Each block includes one or more of the gates. The layout also includes a global routing of the nets. The method also includes performing a first timing analysis of the design and the layout and updating the design and the layout. The method also includes performing a second timing analysis of the design and the layout. The second timing analysis takes into account the updates to the design and the layout. The method also includes, if one or more results of the second timing analysis indicate that the design does not meet one or more predetermined design goals and indicate at least a predetermined amount of progress toward one or more of the design goals relative to the one or more results of the first timing analysis, further updating the design and the layout.
摘要翻译： 在一个实施例中，用于布局驱动的区域约束设计优化的方法包括访问设计的设计和布局。 该设计包括一个或多个栅极和一个或多个将栅极彼此耦合的网络。 布局包括分割设计芯片区域的块。 每个块包括一个或多个门。 布局还包括网络的全局路由。 该方法还包括执行设计和布局的第一时序分析以及更新设计和布局。 该方法还包括执行设计和布局的第二时序分析。 第二个时序分析考虑到设计和布局的更新。 该方法还包括，如果第二定时分析的一个或多个结果指示该设计不符合一个或多个预定设计目标，并且指示相对于该一个或多个设计目标而言朝向一个或多个设计目标的至少预定量的进展 更多结果的第一时间分析，进一步更新设计和布局。
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