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公开(公告)号：US20100049481A1
公开(公告)日：2010-02-25
申请号：US12197572
申请日：2008-08-25
IPC分类号： G06F17/10
CPC分类号： G06F1/10 , G06F17/5036 , G06F2217/62
摘要： A system and method for constructing a clock tree based on replica stages is described. The system and method may comprise determining a size of an input buffer for driving a load capacitance of the output buffer based on a fanout, determining a wire width and a wire length based on the size of the output buffer, the fanout and a replica stage mathematical model, and connecting the output buffer and the corresponding input buffer to a conductor routed on one or more predetermined metal layers and having the wire length and the wire width. The conductor is placed within ground shields having a fixed width.
摘要翻译： 描述了一种基于副本级构建时钟树的系统和方法。 系统和方法可以包括基于扇出来确定用于驱动输出缓冲器的负载电容的输入缓冲器的大小，基于输出缓冲器的大小，扇出和复制级确定线宽度和线长度 数学模型，以及将输出缓冲器和相应的输入缓冲器连接到在一个或多个预定金属层上布线并具有线长度和线宽度的导体。 导体放置在具有固定宽度的接地屏蔽内。
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2.发明授权Border-enhanced sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture 有权边界增强滑动窗口方案（SWS），用于确定基于网格的时钟架构中的时钟时序公开(公告)号：US07788613B2
公开(公告)日：2010-08-31
申请号：US11428995
申请日：2006-07-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh, determining multiple original window locations covering the clock mesh. Each window location includes one or more of the sequential elements on the chip. The method also includes, for each original window location, expanding the original window location in one or more directions to generate a larger window location and generating a mesh simulation model including a detailed model inside the larger window location and an approximate model outside the larger window location, simulating the mesh simulation model, and measuring clock timing for the sequential elements in the window location based on the mesh simulation model. The method also includes collecting timing information on the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.
摘要翻译： 在一个实施例中，一种方法包括访问包括多个顺序元素和时钟网格的芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的一组参数。 该方法还包括使用芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的参数集合，确定覆盖时钟网格的多个原始窗口位置。 每个窗口位置包括芯片上的一个或多个顺序元件。 该方法还包括对于每个原始窗口位置，在一个或多个方向上扩展原始窗口位置以生成更大的窗口位置并生成包括较大窗口位置内的详细模型的网格模拟模型以及较大窗口外的近似模型 位置，模拟网格模拟模型，并基于网格模拟模型测量窗口位置中的顺序元素的时钟时序。 该方法还包括基于原始窗口位置中的顺序元素的测量时钟定时来收集关于芯片上的顺序元件的定时信息。
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公开(公告)号：US08255196B2
公开(公告)日：2012-08-28
申请号：US12197572
申请日：2008-08-25
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G06F17/5036 , G06F2217/62
摘要： A system and method for constructing a clock tree based on replica stages is described. The system and method may comprise determining a size of an input buffer for driving a load capacitance of the output buffer based on a fanout, determining a wire width and a wire length based on the size of the output buffer, the fanout and a replica stage mathematical model, and connecting the output buffer and the corresponding input buffer to a conductor routed on one or more predetermined metal layers and having the wire length and the wire width. The conductor is placed within ground shields having a fixed width.
摘要翻译： 描述了一种基于副本级构建时钟树的系统和方法。 系统和方法可以包括基于扇出来确定用于驱动输出缓冲器的负载电容的输入缓冲器的大小，基于输出缓冲器的大小，扇出和复制级确定线宽度和线长度 数学模型，以及将输出缓冲器和相应的输入缓冲器连接到在一个或多个预定金属层上布线并具有线长度和线宽度的导体。 导体放置在具有固定宽度的接地屏蔽内。
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4.发明授权Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree 有权估计电路的时钟树中的抖动，并合成抖动感知和偏斜感知时钟树公开(公告)号：US07890904B2
公开(公告)日：2011-02-15
申请号：US11421988
申请日：2006-06-02
申请人： Rajeev Murgai , William W. Walker
发明人： Rajeev Murgai , William W. Walker
CPC分类号： G06F1/10 , G06F17/5045
摘要： In one embodiment, a method for computing jitter in a clock tree includes dividing a clock tree into a plurality of stages and computing jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree. The model includes a representation of each source of jitter in the circuit. The method also includes, to compute jitter associated with a path or a pair of paths in the clock tree, statistically combining the jitter in each of the stages of the path or the pair of paths in the clock tree with each other.In one embodiment, to efficiently compute jitter and to achieve zero clock skew, a method synthesizes a symmetrical clock tree of a circuit in which corresponding stages in all paths from a root of the clock tree to sinks of the clock tree exhibit approximate electrical equivalence to each other.
摘要翻译： 在一个实施例中，一种用于计算时钟树中的抖动的方法包括：将时钟树划分成多个级，并且根据与时钟树相关联的电路的至少一部分的模型计算一个或多个级中的抖动 。 该模型包括电路中每个抖动源的表示。 该方法还包括：计算与时钟树中的路径或一对路径相关联的抖动，将时钟树中的路径或路径对中的每个阶段中的抖动统一组合。 在一个实施例中，为了有效地计算抖动并实现零时钟偏移，一种方法合成电路的对称时钟树，其中从时钟树的根到时钟树的汇的所有路径中的相应阶段呈现近似的电等效 彼此。
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5.发明授权Sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture 有权用于确定基于网格的时钟架构中的时钟定时的滑动窗口方案（SWS）公开(公告)号：US07725852B2
公开(公告)日：2010-05-25
申请号：US11428986
申请日：2006-07-06
申请人： Hongyu Chen , William W. Walker , Rajeev Murgai
发明人： Hongyu Chen , William W. Walker , Rajeev Murgai
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/62
摘要： In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh, determining multiple window locations covering the clock mesh. Each window location includes one or more of the sequential elements on the chip. The method also includes, for each window location, generating a mesh simulation model including a detailed model inside the window location and an approximate model outside the window location, simulating the mesh simulation model, and measuring clock timing for the sequential elements in the window location based on the mesh simulation model. The method also includes collecting timing information on the sequential elements on the chip based on the measured clock timing for the sequential elements in the window locations.
摘要翻译： 在一个实施例中，一种方法包括访问包括多个顺序元素和时钟网格的芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的一组参数。 该方法还包括使用芯片的描述，用于建模顺序元件和互连的信息以及时钟网格的参数集，确定覆盖时钟网格的多个窗口位置。 每个窗口位置包括芯片上的一个或多个顺序元件。 该方法还包括对于每个窗口位置，生成包括窗口位置内的详细模型和窗口位置外的近似模型的网格模拟模型，模拟网格模拟模型，以及测量窗口位置中的顺序元素的时钟定时 基于网格模拟模型。 该方法还包括基于窗口位置中的顺序元素的测量时钟定时来收集关于芯片上的顺序元件的定时信息。
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公开(公告)号：US08432995B2
公开(公告)日：2013-04-30
申请号：US12840985
申请日：2010-07-21
申请人： Samir Parikh , Nikola Nedovic , William W. Walker
发明人： Samir Parikh , Nikola Nedovic , William W. Walker
CPC分类号： H04L25/14
摘要： In one embodiment, a method includes receiving input data bits over data channels; receiving deskew channel bits constituting frames that each comprise ones of the input data bits; determining frame boundaries; mapping each of the input data bits in each of the frames to one of the data channels; for each set of the frames, comparing the input data bits in the set with the input data bits in the corresponding input data words; determining relative delays among the data channels and the deskew channel; when non-zero delays are determined, rearranging the input data bits to reduce the delays; and when it is determined that one or more of the data channels have a delay of greater than a predetermined number of data-channel clock periods relative to a particular data channel, delaying input data bits in the particular data channel by an additional number of input data bits.
摘要翻译： 在一个实施例中，一种方法包括：通过数据信道接收输入数据位; 接收构成每个包括所述输入数据位中的一个的帧的歪斜通道位; 确定帧边界; 将每个帧中的每个输入数据位映射到数据信道之一; 对于每组帧，将该组中的输入数据位与相应输入数据字中的输入数据位进行比较; 确定数据通道和歪斜通道之间的相对延迟; 当确定非零延迟时，重新排列输入数据位以减少延迟; 并且当确定一个或多个数据信道相对于特定数据信道具有大于预定数量的数据信道时钟周期的延迟时，通过附加数量的输入来延迟特定数据信道中的输入数据位 数据位。
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公开(公告)号：US20100090733A1
公开(公告)日：2010-04-15
申请号：US12511352
申请日：2009-07-29
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/099 , H03L7/0998 , H04L7/0025 , H04L7/0337
摘要： In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
摘要翻译： 在一个实施例中，电路包括用于接收具有第一相位的第一参考信号的第一电路输入端; 用于接收具有第二相位的第二参考信号的第二电路输入; 用于接收目标相位信号的第三电路输入; 用于输出输出信号的电路输出; 包括第一MMC输入，第二MMC输入和第一MMC输出的第一乘法混频器单元（MMC）; 第二MMC，包括第三MMC输入，第四MMC输入和第二MMC输出。 在示例性实施例中，第一电路输入连接到第一MMC输入; 第二个电路输入连接到第三个MMC输入端; 第三电路输入连接到第二MMC输入和第四MMC输入; 第一MMC输出和第二MMC输出相互组合以提供电路输出; 并且当存在时，输出信号表示与目标相位信号的相位与第一和第二相位的平均值之间的相位差成比例的误差信号。
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公开(公告)号：US07698151B2
公开(公告)日：2010-04-13
申请号：US10335910
申请日：2003-01-03
申请人： Francesco Gozzo , Emmett M. Perry, Jr. , William W. Walker , Michael J. Maselli , James N. Sutton, Jr.
发明人： Francesco Gozzo , Emmett M. Perry, Jr. , William W. Walker , Michael J. Maselli , James N. Sutton, Jr.
IPC分类号： G06Q10/00
摘要： The disaster recovery techniques, for presentment of a company's bills, statements or the like, provide electronic document presentment in the event of a disaster that impacts the company's print mail delivery operation or other existing mailing system(s). Files containing electronic documents are received, from a system associated with the print mail delivery operation, and the documents are stored in a database. Preferably, the systems use the company's existing data files. The files may be converted to a format compatible with one or more electronic delivery methodologies, if necessary. The disaster recovery systems present notice and/or data from the documents to the company's customers electronically, for example as e-mail (notice or message containing some or all of the document data), as a document attachment to an e-mail, via a web site, and possibly via telephone voice announcement.
摘要翻译： 为了呈现公司的账单，陈述等而提供的灾难恢复技术，在发生灾难时提供影响公司打印邮件传送操作或其他现有邮件系统的电子文档呈现。 从与打印邮件传送操作相关联的系统接收包含电子文档的文件，并将文档存储在数据库中。 系统最好使用公司现有的数据文件。 如果需要，这些文件可以被转换成与一种或多种电子传送方法兼容的格式。 灾难恢复系统以电子形式向公司的客户提供文件的通知和/或数据，例如作为电子邮件（包含部分或全部文档数据的通知或消息）作为电子邮件的文档附件，通过 一个网站，并可能通过电话语音通知。
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公开(公告)号：US20090037762A1
公开(公告)日：2009-02-05
申请号：US10335910
申请日：2003-01-03
申请人： Francesco Gozzo , Emmett M. Perry,, JR. , William W. Walker , Michael J. Maselli , James N. Sutton,, JR.
发明人： Francesco Gozzo , Emmett M. Perry,, JR. , William W. Walker , Michael J. Maselli , James N. Sutton,, JR.
摘要： The disaster recovery techniques, for presentment of a company's bills, statements or the like, provide electronic document presentment in the event of a disaster that impacts the company's print mail delivery operation or other existing mailing system(s). Files containing electronic documents are received, from a system associated with the print mail delivery operation, and the documents are stored in a database. Preferably, the systems use the company's existing data files. The files may be converted to a format compatible with one or more electronic delivery methodologies, if necessary. The disaster recovery systems present notice and/or data from the documents to the company's customers electronically, for example as e-mail (notice or message containing some or all of the document data), as a document attachment to an e-mail, via a web site, and possibly via telephone voice announcement.
摘要翻译： 为了呈现公司的账单，陈述等而提供的灾难恢复技术，在发生灾难时提供影响公司打印邮件传送操作或其他现有邮件系统的电子文档呈现。 从与打印邮件传送操作相关联的系统接收包含电子文档的文件，并将文档存储在数据库中。 系统最好使用公司现有的数据文件。 如果需要，这些文件可以被转换成与一种或多种电子传送方法兼容的格式。 灾难恢复系统以电子形式向公司的客户提供文件的通知和/或数据，例如作为电子邮件（包含部分或全部文档数据的通知或消息）作为电子邮件的文档附件，通过 一个网站，并可能通过电话语音通知。
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公开(公告)号：US20080192873A1
公开(公告)日：2008-08-14
申请号：US12022725
申请日：2008-01-30
IPC分类号： H04L7/00
CPC分类号： H04L7/0338
摘要： In one embodiment, a method includes receiving a data signal comprising a plurality of bits. The method further includes generating a clock signal. A plurality of samples is acquired from the data signal at a sampling rate determined by the clock signal and it is determined whether a transition point from a first bit in the plurality of bits to a second bit in the plurality of bits occurs within the plurality of samples. If it is determined that the transition point occurs within the plurality of samples, a state machine comprising a plurality of states transitions from a first state to a second state. If the second state indicates a non-zero amount of phase displacement between the clock signal and the data signal, the clock signal is adjusted to correlate with the data signal.
摘要翻译： 在一个实施例中，一种方法包括接收包括多个比特的数据信号。 该方法还包括产生时钟信号。 从数据信号以由时钟信号确定的采样率获取多个采样，并且确定在多个位中是否发生多个比特中的多个比特中的第一比特到第二比特的转换点 样品。 如果确定在多个样本内发生转换点，则包括多个状态的状态机从第一状态转变到第二状态。 如果第二状态指示时钟信号和数据信号之间的非零相位移量，则调整时钟信号以与数据信号相关。
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