公开(公告)号：US4635190A

公开(公告)日：1987-01-06

申请号：US592870

申请日：1984-03-23

申请人： Willibald Meyer ,  Jurgen Wawersig

发明人： Willibald Meyer ,  Jurgen Wawersig

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/835

摘要： An integrated dynamic write-read memory includes at least one redundant row and/or column initially excluded from normal operation of the memory but available for normal operation as a replacement. At least one row decoder is connected to the memory matrix and at least one column decoder is connected to the memory matrix for addressing. A column address pulse is fed to the memory matrix for initiating addressing by matrix columns and a row address pulse is fed to the memory matrix for initiating addressing by matrix rows. A normal data path leading out of the memory matrix includes a tristate output connected to the normal data path and actuated by addressing with the stored digital data. Another decoder is connected in the normal data path between the memory matrix and the tristate output with an output connected to the tristate output. The other decoder blocks the normal data path from the memory matrix to the tristate output upon addressing each row or column of the portion of the memory matrix intended for normal operation replaced by a redundant row or column and upon simultaneous external activation of the other decoder. The other decoder also indicates the insertion of a redundant row or column in place of a row or column in the portion of the memory matrix intended for normal operation with the appearance of a uniform indicating signal at the data output.

摘要翻译： 集成动态写入存储器包括至少一个冗余行和/或列，其最初从存储器的正常操作中被排除，但可用作正常操作作为替换。 至少一个行解码器连接到存储器矩阵，并且至少一个列解码器连接到用于寻址的存储器矩阵。 列地址脉冲被馈送到存储器矩阵，以通过矩阵列启动寻址，并且行地址脉冲被馈送到存储器矩阵，以通过矩阵行来启动寻址。 从存储矩阵引出的正常数据路径包括连接到正常数据路径的三态输出，并通过利用存储的数字数据进行寻址而致动。 另一个解码器连接在存储器矩阵和三态输出之间的正常数据路径中，输出连接到三态输出。 另一解码器在寻址用于由冗余行或列替代的正常操作的存储器矩阵的部分的每行或列并且在同时外部激活另一个解码器时，将存储器矩阵的正常数据路径阻塞到三态输出。 另一个解码器还指示在数据输出处出现均匀的指示信号的情况下，代替用于正常操作的存储器矩阵的部分中的行或列的冗余行或列的插入。

公开(公告)号：US4737935A

公开(公告)日：1988-04-12

申请号：US759042

申请日：1985-07-25

申请人： Jurgen Wawersig ,  Dieter Kantz

发明人： Jurgen Wawersig ,  Dieter Kantz

IPC分类号： G11C11/401 ,  G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/84

摘要： An integrated write/read memory consisting of a matrix of normal memory cells organized in rows and columns. The memory further includes a smaller matrix of redundant memory cells having their own column and row address decoders that can be engaged to replace any faulty memory cells in the normal matrix. The redundant address decoders are connected to all the address lines by means of fusible links so that any redundant address gate can be programmed to emulate the address of a faulty memory cell. The system further includes logic controls that automatically disables any normal memory address if a redundant memory cell is programmed to take its place.

摘要翻译： 一个由行和列组织的正常存储单元矩阵组成的集成写/读存储器。 存储器还包括具有其自己的列和行地址解码器的冗余存储器单元的较小矩阵，其可以被接合以替换正常矩阵中的任何故障存储器单元。 冗余地址解码器通过可熔链路连接到所有地址线，以便任何冗余地址门可被编程为模拟故障存储单元的地址。 该系统还包括逻辑控制，如果冗余存储单元被编程以占据其位置，则自动禁用任何正常存储器地址。

公开(公告)号：US4602353A

公开(公告)日：1986-07-22

申请号：US554432

申请日：1983-11-21

申请人： Jurgen Wawersig ,  Dieter Kantz

发明人： Jurgen Wawersig ,  Dieter Kantz

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/04 ,  G11C11/409 ,  G11C11/4093 ,  G11C7/00

CPC分类号： G11C7/1024 ,  G11C11/4093 ,  G11C7/1033 ,  G11C8/04

摘要： Integrated semiconductor circuit with a dynamic read-write memory having a memory matrix composed of identical memory cells addressable via row and column decoders with respect to the individual memory cells, the addressing of the individual matrix rows being initiated by a row address strobe while the addressing of the individual matrix columns is initiated by a column address strobe, the addressing being such that during read-out, simultaneously, the information contents of at least two of the memory cells intended for data storage is processed and temporarily stored in an interim register, and including, in addition, a shift register exclusively operated by the column address strobe for the serial transmission of the information contents simultaneously obtained from the memory matrix to the data output of the memory, including means for controlling the data output of the memory via the column address strobe so that the information present at the data output of the memory and made available by the shift register is preserved at the data output of the memory after decay of the column address strobe signal causing readout of the information for a defined time span.

摘要翻译： 具有动态读写存储器的集成半导体电路具有由相对于各个存储器单元经由行和列解码器寻址的相同存储器单元组成的存储器矩阵，各个矩阵行的寻址由行地址选通发起，而寻址 单个矩阵列的列表由列地址选通开始，寻址使得在读出期间同时处理用于数据存储的至少两个存储单元的信息内容并临时存储在临时寄存器中， 并且还包括由列地址选通单独操作的移位寄存器，用于将从存储矩阵同时获得的信息内容串行传输到存储器的数据输出，包括用于经由存储器的数据输出来控制存储器的数据输出的装置 列地址选通，使信息存在于存储器的数据输出端，并使其成为av 在列地址选通信号衰减之后，由存储器的数据输出保存在移位寄存器中，从而在定义的时间间隔内读出信息。