公开(公告)号：US5537352A

公开(公告)日：1996-07-16

申请号：US339515

申请日：1994-11-14

申请人： Willibald Meyer ,  Norbert Wirth

发明人： Willibald Meyer ,  Norbert Wirth

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1087 ,  G11C11/4096 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078

摘要： An integrated semiconductor memory configuration includes a memory region having a plurality of segments. Each of the memory region segments have a plurality of read amplifiers and bit lines. Each two of the bit lines are connected to a respective one of the read amplifiers. A plurality of parallel data lines lead to the memory region. Each of the data lines have an end oriented toward and another end oriented away from a respective one of the memory region segments. Each of a plurality of read/write amplifier switches is disposed at one of the ends of the respective data lines. Each of a plurality of selector switches connects the read/write amplifier switch disposed on the end of a respective one of the data lines oriented toward the memory region segment to a respective one of the read amplifiers of the memory region segment.

摘要翻译： 集成半导体存储器配置包括具有多个段的存储器区域。 每个存储器区段具有多个读取放大器和位线。 位线中的每一个连接到相应的一个读放大器。 多个并行数据线通向存储区域。 每个数据线具有朝向并且另一端朝向远离相应的一个存储器区段的端部。 多个读/写放大器开关中的每一个设置在相应数据线的一端。 多个选择器开关中的每一个将设置在朝向存储区域段的相应一个数据线的端部上的读/写放大器开关连接到存储器区段的读取放大器的相应一个。

公开(公告)号：US5329493A

公开(公告)日：1994-07-12

申请号：US74329

申请日：1993-06-09

申请人： Willibald Meyer ,  Norbert Wirth

发明人： Willibald Meyer ,  Norbert Wirth

IPC分类号： G09G5/00 ,  G09G5/36 ,  G11C7/10 ,  G11C11/401 ,  H04N5/907 ,  G11C13/00

CPC分类号： G11C7/1075 ,  G11C7/103

摘要： An integrated semiconductor memory array includes a memory region, a writing buffer memory associated with the memory region, a writing pointer and an input buffer associated with the writing buffer memory, a reading buffer memory associated with the memory region, a reading pointer and an output buffer associated with the reading buffer memory, and a control device being formed of a memory control circuit and a data flow control circuit. A reading column address decoder controlling the reading pointer is associated with the reading buffer memory. A reading address control unit is connected to the reading column address decoder, and a reading address register is connected to the reading address control unit. A writing column address decoder controlling the writing pointer is associated with the writing buffer memory. A writing address control unit is connected to the writing column address decoder, and a writing address register is connected to the writing address control unit. A line address decoder is provided in the memory control circuit or in the memory region and is triggerable by the reading address control unit and the writing address control unit.

摘要翻译： 集成半导体存储器阵列包括存储器区域，与存储器区域相关联的写入缓冲存储器，写入指针和与写入缓冲存储器相关联的输入缓冲器，与存储器区域相关联的读取缓冲存储器，读取指针和输出 与读取缓冲存储器相关联的缓冲器，以及由存储器控制电路和数据流控制电路构成的控制装置。 控制读取指针的读取列地址解码器与读取缓冲存储器相关联。 读取地址控制单元连接到读取列地址解码器，并且读取地址寄存器连接到读取地址控制单元。 控制写指针的写列地址解码器与写缓冲存储器相关联。 写入地址控制单元连接到写入列地址解码器，并且写入地址寄存器连接到写入地址控制单元。 行地址解码器设置在存储器控制电路或存储器区域中，并且可由读取地址控制单元和写入地址控制单元触发。

公开(公告)号：US5671184A

公开(公告)日：1997-09-23

申请号：US610047

申请日：1996-03-04

申请人： Willibald Meyer

发明人： Willibald Meyer

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C8/00

CPC分类号： G11C29/76

摘要： Memory cells of a semiconductor memory are combined into individually addressable units. An address decoding circuit connects to the units. A programmable address transformation configuration is connected between address terminals receiving external address signals and the decoding circuit. The address transformation configuration, in its unprogrammed state, outputs an internal address signal at each of the outputs which corresponds to the external address signal present at a corresponding one of the address terminals. In its programmed state it outputs an internal address signal at at least one of said outputs, which differs from the external address signal present at a corresponding one of the inputs. The units are thus readdressed relative to the external address. The semiconductor memory is operated by applying external address signals for addressing the units at the address terminals; the external address signals are transformed in an address transformation to become internal address signals within the semiconductor memory. The internal address is fed to the address decoding circuit instead of the external address signals. The address transformation is processed in such a way that, upon application of a first address with a predetermined address value to the address terminals, a different unit is addressed than when the external address were applied without carrying out the address transformation.

摘要翻译： 半导体存储器的存储单元被组合成单独可寻址单元。 地址解码电路连接到单元。 可编程地址变换配置连接在接收外部地址信号的地址终端和解码电路之间。 在其未编程状态下的地址变换配置在对应于存在于对应的一个地址端子处的外部地址信号的每个输出处输出内部地址信号。 在其编程状态下，它在所述输出中的至少一个上输出内部地址信号，该输入与存在于相应输入端的外部地址信号不同。 因此，单元相对于外部地址被读取。 半导体存储器通过施加用于寻址地址端子上的单元的外部地址信号来操作; 外部地址信号在地址变换中变换成半导体存储器内部的地址信号。 内部地址被馈送到地址解码电路，而不是外部地址信号。 以这样的方式对地址变换进行处理，即当将具有预定地址值的第一地址应用于地址终端时，寻址不同于在不执行地址变换的情况下应用外部地址时的不同单元。

公开(公告)号：US4635190A

公开(公告)日：1987-01-06

申请号：US592870

申请日：1984-03-23

申请人： Willibald Meyer ,  Jurgen Wawersig

发明人： Willibald Meyer ,  Jurgen Wawersig

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/835

摘要： An integrated dynamic write-read memory includes at least one redundant row and/or column initially excluded from normal operation of the memory but available for normal operation as a replacement. At least one row decoder is connected to the memory matrix and at least one column decoder is connected to the memory matrix for addressing. A column address pulse is fed to the memory matrix for initiating addressing by matrix columns and a row address pulse is fed to the memory matrix for initiating addressing by matrix rows. A normal data path leading out of the memory matrix includes a tristate output connected to the normal data path and actuated by addressing with the stored digital data. Another decoder is connected in the normal data path between the memory matrix and the tristate output with an output connected to the tristate output. The other decoder blocks the normal data path from the memory matrix to the tristate output upon addressing each row or column of the portion of the memory matrix intended for normal operation replaced by a redundant row or column and upon simultaneous external activation of the other decoder. The other decoder also indicates the insertion of a redundant row or column in place of a row or column in the portion of the memory matrix intended for normal operation with the appearance of a uniform indicating signal at the data output.

摘要翻译： 集成动态写入存储器包括至少一个冗余行和/或列，其最初从存储器的正常操作中被排除，但可用作正常操作作为替换。 至少一个行解码器连接到存储器矩阵，并且至少一个列解码器连接到用于寻址的存储器矩阵。 列地址脉冲被馈送到存储器矩阵，以通过矩阵列启动寻址，并且行地址脉冲被馈送到存储器矩阵，以通过矩阵行来启动寻址。 从存储矩阵引出的正常数据路径包括连接到正常数据路径的三态输出，并通过利用存储的数字数据进行寻址而致动。 另一个解码器连接在存储器矩阵和三态输出之间的正常数据路径中，输出连接到三态输出。 另一解码器在寻址用于由冗余行或列替代的正常操作的存储器矩阵的部分的每行或列并且在同时外部激活另一个解码器时，将存储器矩阵的正常数据路径阻塞到三态输出。 另一个解码器还指示在数据输出处出现均匀的指示信号的情况下，代替用于正常操作的存储器矩阵的部分中的行或列的冗余行或列的插入。

公开(公告)号：US4588907A

公开(公告)日：1986-05-13

申请号：US610092

申请日：1984-05-14

申请人： Willibald Meyer ,  Jurgen Warwersig

发明人： Willibald Meyer ,  Jurgen Warwersig

IPC分类号： G11C29/00 ,  G01R31/317 ,  G06F11/20 ,  G11C11/401 ,  G11C29/14 ,  G11C29/46 ,  G11C29/48 ,  H03K17/693

CPC分类号： G11C29/48 ,  G01R31/31701 ,  G11C29/46

摘要： For integrated digital MOS semiconductor circuits having redundant circuit parts, particularly for semiconductor memories having redundant rows and columns, it is desirable after the employment of the redundant circuit parts to be able to distinguish such a module from those modules in which such an employment of redundant circuit parts has not yet occurred. According to the invention, signals are enabled which serve for the normal mode as well as for the test mode to be input into the circuit via the same signal input. Test signals are distinguished from the other signals by an elevated signal level. The circuit according to the invention includes a circuit part to be activated by means of interrupting a conductive connection, said circuit part then distinguishing the signals applied to the input from one another on the basis of their levels and generating secondary signals on the basis of the signals having the elevated level, said secondary signals then being provided for the control of the test mode.

摘要翻译： 对于具有冗余电路部分的集成数字MOS半导体电路，特别是对于具有冗余行和列的半导体存储器，在使用冗余电路部件之后，希望能够将这样的模块与其中使用冗余的模块区分开 电路部分尚未发生。 根据本发明，启用用于正常模式的信号以及通过相同的信号输入将测试模式输入到电路中。 通过升高的信号电平将测试信号与其他信号区分开来。 根据本发明的电路包括通过中断导电连接而被激活的电路部分，然后所述电路部分基于它们的电平来区分施加到输入端的信号，并基于它们产生次级信号 具有升高电平的信号，然后提供所述次级信号用于控制测试模式。