Resistive memory
    1.
    发明授权

    公开(公告)号:US11257865B2

    公开(公告)日:2022-02-22

    申请号:US16591944

    申请日:2019-10-03

    Abstract: The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local bit line, source lines, and a shared bit line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local bit line extends in a column direction of the array area. The source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line. The shared bit line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.

    Resistive memory
    2.
    发明授权

    公开(公告)号:US12185554B2

    公开(公告)日:2024-12-31

    申请号:US17574422

    申请日:2022-01-12

    Abstract: The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local source line, bit lines, and a shared source line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local source line extends in a column direction of the array area. The bit lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared source line is connected to the local source line. The shared source line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.

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