公开(公告)号：US11908953B2

公开(公告)日：2024-02-20

申请号：US18081703

申请日：2022-12-15

申请人： Winbond Electronics Corp.

发明人： Che-Jui Hsu ,  Ying-Fu Tung ,  Chun-Sheng Lu ,  Kuo-Feng Huang ,  Yu-Chi Kuo ,  Wang-Ta Li

IPC分类号： H01L29/788 ,  H01L21/26 ,  H01L29/66 ,  H10B41/35

CPC分类号： H01L29/788 ,  H01L29/66825 ,  H10B41/35

摘要： A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.

公开(公告)号：US20230121256A1

公开(公告)日：2023-04-20

申请号：US18081703

申请日：2022-12-15

申请人： Winbond Electronics Corp.

发明人： Che-Jui Hsu ,  Ying-Fu Tung ,  Chun-Sheng Lu ,  Kuo-Feng Huang ,  Yu-Chi Kuo ,  Wang-Ta Li

IPC分类号： H01L29/788 ,  H01L29/66 ,  H10B41/35

摘要： A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.

公开(公告)号：US11575051B2

公开(公告)日：2023-02-07

申请号：US16999022

申请日：2020-08-20

申请人： Winbond Electronics Corp.

发明人： Che-Jui Hsu ,  Ying-Fu Tung ,  Chun-Sheng Lu ,  Kuo-Feng Huang ,  Yu-Chi Kuo ,  Wang-Ta Li

IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L27/11524

摘要： A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.

公开(公告)号：US20210066493A1

公开(公告)日：2021-03-04

申请号：US16999022

申请日：2020-08-20

申请人： Winbond Electronics Corp.

发明人： Che-Jui Hsu ,  Ying-Fu Tung ,  Chun-Sheng Lu ,  Kuo-Feng Huang ,  Yu-Chi Kuo ,  Wang-Ta Li

IPC分类号： H01L29/788 ,  H01L27/11524 ,  H01L29/66

摘要： A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.