公开(公告)号：US08605534B2

公开(公告)日：2013-12-10

申请号：US12878703

申请日：2010-09-09

申请人： Winston Lee ,  Ha Soo Kim

发明人： Winston Lee ,  Ha Soo Kim

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C7/02 ,  G11C8/08

摘要： Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.

公开(公告)号：US06292042B1

公开(公告)日：2001-09-18

申请号：US09295403

申请日：1999-04-21

申请人： Ha Soo Kim ,  Sung Ho Wang ,  Tae Hyung Kim

发明人： Ha Soo Kim ,  Sung Ho Wang ,  Tae Hyung Kim

IPC分类号： H03H1116

CPC分类号： H03K5/151

摘要： A phase splitter is disclosed for preventing a timing loss from a presentation timing mismatch of a clock signal of a phase equal to a reference signal and a clock signal of a phase inverted from the reference signal, including a semiconductor device for providing a signal of the same phase and a signal of an inverted phase with respect to a received reference signal, the semiconductor device including a first and a second transmission gates for receiving the reference signal and an inverted version of the received reference signal, and a third and a fourth transmission gates for receiving the reference sign, and the inverted version of that reference signal and for generating a signal having the same phase as the received reference signal and for providing that signal at the same time that the first and second transmission gates provide their output signal, the signals output by the first and second transmission gates having the same timing and opposite phase as the signal output by the third and fourth transmission gates with respect to the reference signal.

摘要翻译： 公开了一种用于防止来自等于参考信号的相位的时钟信号的呈现定时失配的定时损失和与参考信号相反的相位的时钟信号的定时损耗，包括用于提供信号的信号的半导体器件 相位相位和相对于接收的参考信号的反相信号，所述半导体器件包括用于接收参考信号的第一和第二传输门和所接收的参考信号的反相形式，以及第三和第四传输 用于接收参考符号的门和该参考信号的反相版本，并用于产生具有与接收到的参考信号相同相位的信号，并且用于在第一和第二传输门提供其输出信号的同时提供该信号， 由第一和第二传输门输出的信号具有与由t输出的信号相同的定时和相反相位 他相对于参考信号的第三和第四传输门。