METHOD OF MANUFACTURING A FINNED SEMICONDUCTOR DEVICE STRUCTURE
    1.
    发明申请
    METHOD OF MANUFACTURING A FINNED SEMICONDUCTOR DEVICE STRUCTURE 有权
    制造精细半导体器件结构的方法

    公开(公告)号:US20110237046A1

    公开(公告)日:2011-09-29

    申请号:US12749220

    申请日:2010-03-29

    IPC分类号: H01L21/762

    CPC分类号: H01L29/66545 H01L29/66795

    摘要: A method of manufacturing a finned semiconductor device structure is provided. The method begins by providing a substrate having bulk semiconductor material. The method continues by forming a semiconductor fin structure from the bulk semiconductor material, depositing an insulating material overlying the semiconductor fin structure such that the insulating material fills space adjacent to the semiconductor fin structure, and planarizing the deposited insulating material and the semiconductor fin structure to create a flat surface. Thereafter, a replacement gate procedure is performed to form a gate structure transversely overlying the semiconductor fin structure.

    摘要翻译: 提供一种制造翅片半导体器件结构的方法。 该方法开始于提供具有体半导体材料的衬底。 该方法继续通过从体半导体材料形成半导体鳍结构,沉积覆盖半导体鳍结构的绝缘材料,使得绝缘材料填充与半导体鳍结构相邻的空间,并将沉积的绝缘材料和半导体鳍结构平坦化为 创建一个平坦的表面。 此后,执行替换门程序以形成横向覆盖半导体鳍结构的栅极结构。

    METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL
    2.
    发明申请
    METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL 有权
    在半导体材料上形成分离的结构的方法

    公开(公告)号:US20130005114A1

    公开(公告)日:2013-01-03

    申请号:US13611193

    申请日:2012-09-12

    IPC分类号: H01L21/762

    CPC分类号: H01L29/785 H01L29/66795

    摘要: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

    摘要翻译: 提供了制造半导体器件的方法。 一种方法包括形成覆盖在本体衬底上的第一半导体材料层,并形成覆盖第一半导体材料层的第二半导体材料层。 该方法还包括在第二半导体材料的层上形成鳍状图案掩模,并使用鳍状图案掩模作为蚀刻掩模,各向异性蚀刻第二半导体材料的层和第一半导体材料的层。 各向异性蚀刻导致由第二半导体材料形成的翅片和鳍下方的第一半导体材料的暴露区域。 该方法还包括在鳍片下方的第一半导体材料的暴露区域中形成隔离层。

    METHOD OF FORMING FIN STRUCTURES USING A SACRIFICIAL ETCH STOP LAYER ON BULK SEMICONDUCTOR MATERIAL
    3.
    发明申请
    METHOD OF FORMING FIN STRUCTURES USING A SACRIFICIAL ETCH STOP LAYER ON BULK SEMICONDUCTOR MATERIAL 有权
    在半导体材料上使用极限蚀刻停止层形成晶体结构的方法

    公开(公告)号:US20100248454A1

    公开(公告)日:2010-09-30

    申请号:US12413174

    申请日:2009-03-27

    IPC分类号: H01L21/20 H01L21/28

    CPC分类号: H01L29/66795

    摘要: A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.

    摘要翻译: 制造用于半导体器件的半导体鳍片的方法可以通过提供体半导体衬底开始。 该方法通过在体半导体衬底上生长第一外延半导体材料层并通过在第一外延半导体材料层上生长第二外延半导体材料层来继续。 该方法然后在第二外延半导体材料层上产生鳍状图案掩模。 翅片图形掩模具有对应于多个翅片的特征。 接下来,使用鳍图案掩模作为蚀刻掩模,并且使用第一外延半导体材料层作为蚀刻停止层,该方法各向异性地蚀刻第二外延半导体材料的层。 该蚀刻步骤导致由第二外延半导体材料层形成的多个鳍片。

    METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL
    4.
    发明申请
    METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL 有权
    在半导体材料上形成分离的结构的方法

    公开(公告)号:US20120040517A1

    公开(公告)日:2012-02-16

    申请号:US13278010

    申请日:2011-10-20

    IPC分类号: H01L21/20 H01L21/302

    CPC分类号: H01L29/785 H01L29/66795

    摘要: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

    摘要翻译: 提供了制造半导体器件的方法。 一种方法包括形成覆盖在本体衬底上的第一半导体材料层,并形成覆盖第一半导体材料层的第二半导体材料层。 该方法还包括在第二半导体材料的层上形成鳍状图案掩模,并使用鳍状图案掩模作为蚀刻掩模,各向异性蚀刻第二半导体材料的层和第一半导体材料的层。 各向异性蚀刻导致由第二半导体材料形成的翅片和鳍下方的第一半导体材料的暴露区域。 该方法还包括在鳍片下方的第一半导体材料的暴露区域中形成隔离层。

    METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL
    5.
    发明申请
    METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL 有权
    在半导体材料上形成分离的结构的方法

    公开(公告)号:US20110081764A1

    公开(公告)日:2011-04-07

    申请号:US12575344

    申请日:2009-10-07

    IPC分类号: H01L21/762 H01L21/20

    CPC分类号: H01L29/785 H01L29/66795

    摘要: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

    摘要翻译: 提供了制造半导体器件的方法。 一种方法包括形成覆盖在本体衬底上的第一半导体材料层,并形成覆盖第一半导体材料层的第二半导体材料层。 该方法还包括在第二半导体材料的层上形成鳍状图案掩模,并使用鳍状图案掩模作为蚀刻掩模,各向异性蚀刻第二半导体材料的层和第一半导体材料的层。 各向异性蚀刻导致由第二半导体材料形成的翅片和鳍下方的第一半导体材料的暴露区域。 该方法还包括在鳍片下方的第一半导体材料的暴露区域中形成隔离层。

    THIN BODY SEMICONDUCTOR DEVICES HAVING IMPROVED CONTACT RESISTANCE AND METHODS FOR THE FABRICATION THEREOF
    6.
    发明申请
    THIN BODY SEMICONDUCTOR DEVICES HAVING IMPROVED CONTACT RESISTANCE AND METHODS FOR THE FABRICATION THEREOF 有权
    具有改善的接触电阻的薄体半导体器件及其制造方法

    公开(公告)号:US20110062443A1

    公开(公告)日:2011-03-17

    申请号:US12560938

    申请日:2009-09-16

    申请人: Witold MASZARA

    发明人: Witold MASZARA

    摘要: Embodiments of a method for fabricating a semiconductor device are provided. In one embodiment, the method includes the step of producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, a gate stack over the channel region, and sidewall spacers laterally adjacent the gate stack. The method further includes the steps of amorphizing the S/D regions, depositing a silicide-forming material over the amorphized S/D regions, and heating the partially-completed semiconductor device to a predetermined temperature at which the silicide-forming material reacts with the amorphized S/D regions.

    摘要翻译: 提供了制造半导体器件的方法的实施例。 在一个实施例中,该方法包括产生部分完成的半导体器件的步骤,该半导体器件包括衬底,源极/漏极(S / D)区域,S / D区域之间的沟道区域,沟道区域上的栅极堆叠,以及 横向隔离件横向邻近门堆叠。 该方法还包括以下步骤:使S / D区域非晶化,在非晶化S / D区域上沉积硅化物形成材料,并将部分完成的半导体器件加热至预定温度,在该温度下硅化物形成材料与 非晶化S / D区域。