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1.发明授权Memory circuit arrangement with a cell array substrate and a logic circuit substrate and method for the production thereof 有权具有单元阵列基板和逻辑电路基板的存储器电路布置及其制造方法公开(公告)号：US07460385B2
公开(公告)日：2008-12-02
申请号：US11251355
申请日：2005-10-14
CPC分类号： G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： In a memory circuit arrangement and fabrication method, the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
摘要翻译： 在存储器电路布置和制造方法中，存储器电路装置的部分位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。
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公开(公告)号：US08105874B2
公开(公告)日：2012-01-31
申请号：US12258742
申请日：2008-10-27
IPC分类号： H01L21/00
CPC分类号： G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
摘要翻译： 提出了一种存储器电路装置及其制造方法，其中存储器电路装置的部件位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。
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公开(公告)号：US08004869B2
公开(公告)日：2011-08-23
申请号：US12772590
申请日：2010-05-03
CPC分类号： G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
摘要翻译： 提出了一种存储器电路装置及其制造方法，其中存储器电路装置的部件位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。
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公开(公告)号：US20090053854A1
公开(公告)日：2009-02-26
申请号：US12258742
申请日：2008-10-27
IPC分类号： H01L21/00
CPC分类号： G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
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公开(公告)号：US20080239863A1
公开(公告)日：2008-10-02
申请号：US12135687
申请日：2008-06-09
IPC分类号： G11C8/10
CPC分类号： G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： In a memory circuit arrangement and fabrication method, the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
摘要翻译： 在存储器电路布置和制造方法中，存储器电路装置的部分位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。
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公开(公告)号：US20060077723A1
公开(公告)日：2006-04-13
申请号：US11251355
申请日：2005-10-14
IPC分类号： G11C16/04
CPC分类号： G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
摘要翻译： 提出了一种存储器电路装置及其制造方法，其中存储器电路装置的部件位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。
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公开(公告)号：US20090052219A1
公开(公告)日：2009-02-26
申请号：US12258728
申请日：2008-10-27
CPC分类号： G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
摘要翻译： 提出了一种存储器电路装置及其制造方法，其中存储器电路装置的部件位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。
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公开(公告)号：US20100210076A1
公开(公告)日：2010-08-19
申请号：US12772590
申请日：2010-05-03
IPC分类号： H01L21/82
CPC分类号： G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
摘要翻译： 提出了一种存储器电路装置及其制造方法，其中存储器电路装置的部件位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。
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公开(公告)号：US07764530B2
公开(公告)日：2010-07-27
申请号：US12258728
申请日：2008-10-27
CPC分类号： G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
摘要翻译： 提出了一种存储器电路装置及其制造方法，其中存储器电路装置的部件位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。
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10.发明申请FLUORESCENT COATING FOR HIGH OUTPUT LAMPS WITH COLOR TEMPERATURES OF LESS THAN 2700 KELVIN 失效用于高输出灯的荧光涂层，颜色温度低于2700 KELVIN公开(公告)号：US20100052507A1
公开(公告)日：2010-03-04
申请号：US12312007
申请日：2007-10-22
CPC分类号： H01J61/44 , C09K11/778 , C09K11/7787
摘要： The invention relates to a fluorescent coating for Hg low-pressure discharge lamps, comprising a fluorescent composition from at least one green fluorescent material emitting in the green spectral range, especially a Tb- and/or Eu-doped green fluorescent material, and a red fluorescent material emitting in the red spectral range, especially a Eu and/or Mn red fluorescent material. The invention is characterized in that a further fluorescent material is present which is adapted to absorb UV Hg and Hg-Vis radiation.
摘要翻译： 本发明涉及一种用于Hg低压放电灯的荧光涂层，其包括由绿色光谱范围内发射的至少一种绿色荧光材料的荧光组合物，特别是Tb掺杂和/或Eu掺杂的绿色荧光材料，以及红 在红色光谱范围内发射的荧光材料，特别是Eu和/或Mn红色荧光材料。 本发明的特征在于存在适于吸收UV Hg和Hg-Vis辐射的另外的荧光材料。
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