Method and apparatus for adaptive verification of circuit designs
    1.
    发明授权
    Method and apparatus for adaptive verification of circuit designs 有权
    电路设计自适应验证的方法和装置

    公开(公告)号:US06427223B1

    公开(公告)日:2002-07-30

    申请号:US09303181

    申请日:1999-04-30

    IPC分类号: G06F1750

    CPC分类号: G06F17/5022

    摘要: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the monitoring of a device under test (DUT). The HVL language supports Object-Oriented Programming (or OOP). Within this OOP framework, the present invention provides a monitoring facility comprised of three main stages: i) Coverage Definitions, ii) Coverage Instantiation and Triggering and iii) Coverage Feedback. A coverage definition is very similar to an OOP class definition, but does not contain methods or variables. Instead, the basic purpose of a coverage definition is to declare “monitor bins” in terms of a state variable. Essentially, each monitor bin declaration has a unique bin name which is associated with a particular behavior of the state variable and the unique bin name is used to record the state variable's behavior. Instantiation of a coverage definition produces a coverage instance. Two key instantiation parameters are: an actual state variable that is to be monitored by the instance and a trigger expression which determines when the state variable of the instance is to be monitored. Instantiating means that a concurrent, non-terminating, “coverage instance process” is also forked off. The “foreground” thread of control which forked off the coverage instance process may continue to operate and subject a DUT to stimuli. The DUT's responses to such stimuli may be monitored by the coverage instance process and stored as data associated with the coverage instance. The same foreground thread of control subjecting the DUT to stimuli can also query the resulting state of the coverage instance's data. This ability to query a coverage instance's data make possible “closed loop” testing since the foreground thread of control can subsequently alter further stimuli generated for the DUT based upon the results of its query.

    摘要翻译: 本发明将硬件验证语言(HVL)的功能添加到便于监视被测器件(DUT)的功能。 HVL语言支持面向对象编程(或OOP)。 在本OOP框架内,本发明提供了一个由三个主要阶段组成的监测设施:i)覆盖定义,ii)覆盖实例化和触发,以及iii)覆盖反馈。 覆盖定义与OOP类定义非常相似,但不包含方法或变量。 相反,覆盖定义的基本目的是根据状态变量声明“监视器仓”。 基本上,每个监视器bin声明都有一个唯一的bin名称,它与状态变量的特定行为相关联,唯一的bin名称用于记录状态变量的行为。 覆盖定义的实例化生成coverage实例。 两个关键的实例化参数是:要由实例监视的实际状态变量和确定何时要监视实例的状态变量的触发器表达式。 实例化意味着并发,非终止的“覆盖实例进程”也被分支。 分离覆盖实例过程的“前景”控制线程可以继续操作并使DUT受到刺激。 DUT对这种刺激的响应可以由覆盖实例过程来监视,并且被存储为与覆盖实例相关联的数据。 对DUT进行刺激的相同前景控制线程也可以查询覆盖实例的数据的结果状态。 查询coverage实例的数据的这种能力使得“闭环”测试成为可能,因为控制的前台线程可随后根据其查询结果改变为DUT产生的进一步刺激。

    Method and apparatus for random stimulus generation
    2.
    发明授权
    Method and apparatus for random stimulus generation 有权
    随机刺激生成的方法和装置

    公开(公告)号:US06513144B1

    公开(公告)日:2003-01-28

    申请号:US09298984

    申请日:1999-04-22

    IPC分类号: G06F1750

    摘要: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. If a constraint block of an instance is active or ON, then all the constraint expressions in the block will act to constrain their lhs random variable. A constraint block which is OFF means that all of its constraint expressions will not act to constrain their random variables. The method “constraint_mode” can be used to turn ON or OFF any constraint blocks of an instance.

    摘要翻译: 本发明增加了便于生成随机测试数据的硬件验证语言(HVL)的功能。 通过简单地将随机属性添加到类定义的变量声明来容易地产生随机数的来源。 这些变量称为随机变量。 可以对类定义的实例进行“randomize”方法调用,以产生每个随机变量的随机值。 分配给随机变量的值使用约束块进行控制,约束块是类定义的一部分。 约束块由约束表达式组成,其中每个约束表达式限制可以分配给约束表达式左侧(lhs)的随机变量的值。 如果实例的约束块处于活动状态或ON状态,则块中的所有约束表达式将用于约束其lhs随机变量。 一个约束块是OFF表示它的所有约束表达式都不会用来约束它们的随机变量。 方法“constraint_mode”可用于打开或关闭实例的任何约束块。

    Method and apparatus for random stimulus generation
    3.
    发明授权
    Method and apparatus for random stimulus generation 有权
    随机刺激生成的方法和装置

    公开(公告)号:US07900111B1

    公开(公告)日:2011-03-01

    申请号:US10420443

    申请日:2003-04-21

    IPC分类号: G01R31/28 G06F11/00

    摘要: Capabilities are added to a Hardware Verification Language that facilitates the generation of test data. Random number sources, called random variables, can be produced by adding a randomness attribute to a variable declaration of a class definition. A “randomize” method call to a class instance produces a random value for each random variable. Constraint blocks, of a class definition, control random variables with constraint expressions. Dependency, of random variable value assignment, as determined by constraint expressions, can be expressed by a DAG. A constraint expression is converted into ranges of permissible values, from which a value is randomly chosen by a randomize method. A “boundary” method call sequentially selects a combination of boundary values, for each random variable, from each random variable's set of ranges. Coordinated selection of a boundary values permits all combinations of boundary values to be produced through successive boundary calls.

    摘要翻译: 功能被添加到便于生成测试数据的硬件验证语言。 随机数字源,称为随机变量,可以通过将随机属性添加到类定义的变量声明来生成。 对类实例的“randomize”方法调用会为每个随机变量产生一个随机值。 类定义的约束块用约束表达式控制随机变量。 由约束表达式确定的随机变量值分配的依赖性可由DAG表示。 约束表达式转换为允许值的范围,随机选择一个值。 “边界”方法调用从每个随机变量的范围集合中顺序地选择每个随机变量的边界值的组合。 边界值的协调选择允许通过连续边界调用产生边界值的所有组合。

    Method and apparatus for random stimulus generation
    4.
    发明授权
    Method and apparatus for random stimulus generation 有权
    随机刺激生成的方法和装置

    公开(公告)号:US06553531B1

    公开(公告)日:2003-04-22

    申请号:US09344148

    申请日:1999-06-24

    IPC分类号: G01R3128

    摘要: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions. The constraint expressions may impose a linear ordering in which random variable values must be assigned and this dependency is expressed by directed acyclic graphs (DAGs). The constraint expressions constraining each random variable are converted into ranges of permissible values from which a value is chosen at random. Rather than selecting a value for each random variable from within one of its ranges, as done for the randomize method, each boundary method call sequentially selects a combination of boundary values, for each random variable, from each random variable's set of ranges. By selecting a boundary value for each random variable of the instance, in a coordinated fashion, all combinations of boundary values can be produced through successive calls to the boundary function. As with the randomize method, since random variables may depend upon each other, the selection of a boundary value for one random variable may change the selection of boundary values available for other random variables.

    摘要翻译: 本发明增加了便于生成随机测试数据的硬件验证语言(HVL)的功能。 通过简单地将随机属性添加到类定义的变量声明来容易地产生随机数的来源。 这些变量称为随机变量。 可以对类定义的实例进行“randomize”方法调用,以产生每个随机变量的随机值。 分配给随机变量的值使用约束块进行控制,约束块是类定义的一部分。 约束块由约束表达式组成。 约束表达式可以强加一个线性排序,其中必须分配随机变量值,并且该依赖关系由有向非循环图(DAG)表示。 约束每个随机变量的约束表达式被转换为随机选择值的允许值的范围。 每个边界方法调用从每个随机变量的每个随机变量集合中顺序地选择边界值的组合,而不是从其范围之一内选择每个随机变量的值。 通过以协调的方式选择实例的每个随机变量的边界值,可以通过对边界函数的连续调用来产生边界值的所有组合。 与随机化方法一样,由于随机变量可能依赖于彼此,所以对一个随机变量的边界值的选择可以改变对其他随机变量可用的边界值的选择。

    Method and apparatus for random stimulus generation
    5.
    发明授权
    Method and apparatus for random stimulus generation 有权
    随机刺激生成的方法和装置

    公开(公告)号:US06499127B1

    公开(公告)日:2002-12-24

    申请号:US09298986

    申请日:1999-04-22

    IPC分类号: G01R3128

    摘要: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. A constraint_expression can constrain any random variable which has been declared at its level in the class hierarchy, or at any higher level. A constraint_expression cannot constrain a random variable declared at a lower level in the hierarchy. If a constraint block of an instance is active or ON, then all the constraint expressions in the block will act to constrain their lhs random variable. A constraint block which is OFF means that all of its constraint expressions will not act to constrain their random variables. The method “constraint_mode” can be used to turn ON or OFF any constraint blocks of an instance. The effects of a constraint block can be completely eliminated by defining, at a lower level in the hierarchy, another constraint block with the same name.

    摘要翻译: 本发明增加了便于生成随机测试数据的硬件验证语言(HVL)的功能。 通过简单地将随机属性添加到类定义的变量声明来容易地产生随机数的来源。 这些变量称为随机变量。 可以对类定义的实例进行“randomize”方法调用,以产生每个随机变量的随机值。 分配给随机变量的值使用约束块进行控制,约束块是类定义的一部分。 约束块由约束表达式组成,其中每个约束表达式限制可以分配给约束表达式左侧(lhs)的随机变量的值。 constraint_expression可以限制已经在类层次结构或其他更高层级声明的任何随机变量。 constraint_expression不能限制层次结构中较低级别声明的随机变量。 如果实例的约束块处于活动状态或ON状态,则块中的所有约束表达式将用于约束其lhs随机变量。 一个约束块是OFF表示它的所有约束表达式都不会用来约束它们的随机变量。 方法“constraint_mode”可用于打开或关闭实例的任何约束块。 通过在层次结构中的较低级别定义具有相同名称的另一个约束块,可以完全消除约束块的影响。

    Method and apparatus for determining expected values during circuit design verification
    6.
    发明授权
    Method and apparatus for determining expected values during circuit design verification 有权
    用于在电路设计验证期间确定期望值的方法和装置

    公开(公告)号:US06493841B1

    公开(公告)日:2002-12-10

    申请号:US09283774

    申请日:1999-03-31

    IPC分类号: G01R3128

    CPC分类号: G06F17/5022

    摘要: Hardware Verification Languages (HVLs) permit the convenient modeling of the environment for a device under test (DUT). HVLs permit the DUT to be tested by stimulating certain inputs of the DUT and monitoring the resulting states of the DUT. The present invention relates to an HVL, referred to as Vera, for the verification of any form of digital circuit design. Vera is preferably used for testing a DUT modeled in a high-level hardware description language (HLHDL) such as Verilog HDL. More specifically, the present invention relates to an HVL capability, know as an “expect,” for monitoring the values at certain nodes of the DUT at certain times and for determining whether those values are in accordance with the DUT's expected performance. In particular, upon the first occurrence of a transition on one of the DUT's nodes, since beginning a window period of monitoring, the expect will either generate an error if the DUT's output is unexpected, or proceed with modeling the DUT's environment if the output is expected. A delay may be specified, which will delay the expect's initiation of the window monitoring period.

    摘要翻译: 硬件验证语言(HVL)允许对被测设备(DUT)的环境进行便利建模。 HVL允许通过激发DUT的某些输入并监测DUT的结果状态来测试DUT。 本发明涉及一种称为Vera的HVL,用于验证任何形式的数字电路设计。 Vera优选用于测试以诸如Verilog HDL的高级硬件描述语言(HLHDL)建模的DUT。 更具体地说,本发明涉及一种被称为“期望”的HVL能力,用于监视在某些特定时间的DUT的某些节点处的值,并且确定这些值是否符合DUT的预期性能。 特别是,在DUT的一个节点上首次发生转换时,由于开始监视的窗口周期,如果DUT的输出是意外的,则期望会产生错误,或者如果输出为 预期。 可以指定延迟,这将延迟预期启动窗口监视周期。

    Method and apparatus for random stimulus generation
    7.
    发明授权
    Method and apparatus for random stimulus generation 有权
    随机刺激生成的方法和装置

    公开(公告)号:US06449745B1

    公开(公告)日:2002-09-10

    申请号:US09298981

    申请日:1999-04-22

    IPC分类号: G01R3128

    摘要: The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the generation of random test data. Sources of random numbers are easily produced by simply adding a randomness attribute to a variable declaration of a class definition. Such variables are called random variables. A “randomize” method call may be made to an instance of the class definition to produce random values for each random variable. The values assigned to random variables are controlled using constraint blocks, which are part of the class definition. A constraint block is comprised of constraint expressions, where each constraint expression limits the values that can be assigned to a random variable on the left-hand-side (lhs) of the constraint expression. Because random variables may also appear on the right-hand-side (rhs) of a constraint expression there is an ordering in which random variable values must be assigned and this dependency is expressed by directed acyclic graphs (DAGs). A linear ordering for assigning values to the random variables is derived from the DAGs. The constraint expressions constraining each random variable are converted into ranges of permissible values from which a value is chosen at random.

    摘要翻译: 本发明增加了便于生成随机测试数据的硬件验证语言(HVL)的功能。 通过简单地将随机属性添加到类定义的变量声明来容易地产生随机数的来源。 这些变量称为随机变量。 可以对类定义的实例进行“randomize”方法调用,以产生每个随机变量的随机值。 分配给随机变量的值使用约束块进行控制,约束块是类定义的一部分。 约束块由约束表达式组成,其中每个约束表达式限制可以分配给约束表达式左侧(lhs)的随机变量的值。 因为随机变量也可能出现在约束表达式的右侧(rhs),所以存在必须分配随机变量值的顺序,并且这种依赖关系由有向无环图(DAG)表示。 从DAG派生用于将值分配给随机变量的线性排序。 约束每个随机变量的约束表达式被转换为随机选择值的允许值的范围。

    Intubation device with variable backflow pressure

    公开(公告)号:US10179219B2

    公开(公告)日:2019-01-15

    申请号:US15487235

    申请日:2017-04-13

    摘要: Intubation devices, systems, and methods in which the risk of leakage of nasopharyngeal secretions, esophageal reflux, and blood is reduced, or eliminated, by means of a backflow pressure gradient that is independent of PEEP. Contemplated configurations include (a) a flexible tube for the controlled delivery of air and other gases to the lungs, (b) distal and proximal inflatable seals that can close the annular space surrounding the tube, (c) means to inflate the seals, and (d) means to deliver gas under pressure to the annular chamber in between the two seals. Further configurations further comprise a processor and sensors, and methods are provided for automated backflow of contaminated fluids.

    Intubation Device with Variable Backflow Pressure

    公开(公告)号:US20180296782A1

    公开(公告)日:2018-10-18

    申请号:US15487235

    申请日:2017-04-13

    IPC分类号: A61M16/04 A61M16/20

    摘要: Intubation devices, systems, and methods in which the risk of leakage of nasopharyngeal secretions, esophageal reflux, and blood is reduced, or eliminated, by means of a backflow pressure gradient that is independent of PEEP. Contemplated configurations include (a) a flexible tube for the controlled delivery of air and other gases to the lungs, (b) distal and proximal inflatable seals that can close the annular space surrounding the tube, (c) means to inflate the seals, and (d) means to deliver gas under pressure to the annular chamber in between the two seals. Further configurations further comprise a processor and sensors, and methods are provided for automated backflow of contaminated fluids.