公开(公告)号：US08522114B2

公开(公告)日：2013-08-27

申请号：US12768047

申请日：2010-04-27

申请人： Woo tae Chang ,  Yong tae Yim

发明人： Woo tae Chang ,  Yong tae Yim

IPC分类号： G11C29/00

CPC分类号： G06F11/1048

摘要： A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory.

摘要翻译： 提供了一种存储系统。 存储器系统包括非易失性存储器和控制器。 非易失性存储器包括存储单元阵列和被配置为在读取操作期间在存储单元阵列中执行读/写操作的读/写电路。 控制器被配置为从非易失性存储器接收读取的数据，对读取的数据执行错误检测和校正操作。 在检测到所读取的数据的接收部分中的错误时，控制器还被配置为停止从非易失性存储器进一步发送读取的数据，对读取的数据的接收部分执行错误检测和校正操作，以校正检测到的 错误。 在读取数据的接收部分中校正检测到的错误之后，控制器被配置为恢复从非易失性存储器发送读取的数据。