公开(公告)号：US6130457A

公开(公告)日：2000-10-10

申请号：US192125

申请日：1998-11-13

Applicant: Sun-il Yu ,  Woo-tag Kang

Inventor： Sun-il Yu ,  Woo-tag Kang

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L29/78603 ,  H01L29/78612 ,  H01L21/76272 ,  H01L21/76281 ,  Y10S438/977

Abstract: Methods of forming semiconductor-on-insulator substrates include the steps of forming a underlying semiconductor layer to electrically interconnect a plurality of SOI active regions and thereby prevent one or more of the active regions from "floating" relative to the other active regions. The reduction of floating body effects (FBE) improves the I-V characteristics of SOI devices including SOI MOSFETs. A method is provided which includes the steps of forming a second electrically insulating layer having a plurality of first openings therein, on a first face of a first semiconductor substrate. A first semiconductor layer is then formed on the second electrically insulating layer so that direct electrical connections are made between the first semiconductor layer and the first semiconductor substrate. A first electrically insulating layer is then formed on the first semiconductor layer. This first electrically insulating layer is then planarized and bonded to a second semiconductor substrate. The composite intermediate structure is then inverted and followed by the step of planarizing a second face of the first semiconductor substrate to define a second semiconductor layer. A plurality of spaced semiconductor active regions are then defined in the second semiconductor layer by using field oxide isolation techniques to consume the entire thickness of the second semiconductor layer at predetermined spaced locations. This step essentially isolates the active regions from each other, however, these active regions do not "float" because they are electrically connected to each other indirectly through the underlying first semiconductor layer.

Abstract translation: 形成绝缘体上半导体衬底的方法包括以下步骤：形成下面的半导体层以电连接多个SOI有源区，从而防止一个或多个有源区相对于其它有源区“漂浮”。 浮体效应（FBE）的降低提高了包括SOI MOSFET在内的SOI器件的I-V特性。 提供了一种方法，其包括在第一半导体衬底的第一面上形成其中具有多个第一开口的第二电绝缘层的步骤。 然后在第二电绝缘层上形成第一半导体层，使得在第一半导体层和第一半导体衬底之间形成直接电连接。 然后在第一半导体层上形成第一电绝缘层。 然后将该第一电绝缘层平坦化并结合到第二半导体衬底。 然后将复合中间结构反转，随后平面化第一半导体衬底的第二面以限定第二半导体层的步骤。 然后通过使用场氧化物隔离技术在第二半导体层中限定多个间隔的半导体有源区，以在预定的间隔位置消耗第二半导体层的整个厚度。 该步骤基本上将活性区域彼此隔离，然而，这些活性区域不会“浮动”，因为它们通过下面的第一半导体层间接地彼此电连接。

公开(公告)号：US5877046A

公开(公告)日：1999-03-02

申请号：US835605

申请日：1997-04-09

Applicant: Sun-il Yu ,  Woo-tag Kang

Inventor： Sun-il Yu ,  Woo-tag Kang

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L29/78603 ,  H01L29/78612 ,  H01L21/76272 ,  H01L21/76281 ,  Y10S438/977

Abstract: Methods of forming semiconductor-on-insulator substrates include the steps of forming a underlying semiconductor layer to electrically interconnect a plurality of SOI active regions and thereby prevent one or more of the active regions from "floating" relative to the other active regions. The reduction of floating body effects (FBE) improves the I-V characteristics of SOI devices including SOI MOSFETs. A method is provided which includes the steps of forming a second electrically insulating layer having a plurality of first openings therein, on a first face of a first semiconductor substrate. A first semiconductor layer is then formed on the second electrically insulating layer so that direct electrical connections are made between the first semiconductor layer and the first semiconductor substrate. A first electrically insulating layer is then formed on the first semiconductor layer. This first electrically insulating layer is then planarized and bonded to a second semiconductor substrate. The composite intermediate structure is then inverted and followed by the step of planarizing a second face of the first semiconductor substrate to define a second semiconductor layer. A plurality of spaced semiconductor active regions are then defined in the second semiconductor layer by using field oxide isolation techniques to consume the entire thickness of the second semiconductor layer at predetermined spaced locations. This step essentially isolates the active regions from each other, however, these active regions do not "float" because they are electrically connected to each other indirectly through the underlying first semiconductor layer.

Abstract translation: 形成绝缘体上半导体衬底的方法包括以下步骤：形成下面的半导体层以电连接多个SOI有源区，从而防止一个或多个有源区相对于其它有源区“漂浮”。 浮体效应（FBE）的降低提高了包括SOI MOSFET在内的SOI器件的I-V特性。 提供了一种方法，其包括在第一半导体衬底的第一面上形成其中具有多个第一开口的第二电绝缘层的步骤。 然后在第二电绝缘层上形成第一半导体层，使得在第一半导体层和第一半导体衬底之间形成直接电连接。 然后在第一半导体层上形成第一电绝缘层。 然后将该第一电绝缘层平坦化并结合到第二半导体衬底。 然后将复合中间结构反转，随后平面化第一半导体衬底的第二面以限定第二半导体层的步骤。 然后通过使用场氧化物隔离技术在第二半导体层中限定多个间隔的半导体有源区，以在预定的间隔位置消耗第二半导体层的整个厚度。 该步骤基本上将活性区域彼此隔离，然而，这些活性区域不会“浮动”，因为它们通过下面的第一半导体层间接地彼此电连接。

公开(公告)号：US06724054B1

公开(公告)日：2004-04-20

申请号：US10320867

申请日：2002-12-17

Applicant: Woo-tag Kang ,  Rajeev Malik ,  Mihel Seitz

Inventor： Woo-tag Kang ,  Rajeev Malik ,  Mihel Seitz

IPC: H01L31119

CPC classification number: H01L21/76897 ,  H01L29/6656

Abstract: A method for fabricating a self-aligned contact in an integrated circuit includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and which cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.

Abstract translation: 在集成电路中制造自对准接触的方法包括在一对字线堆叠的侧壁上限定第一间隔层。 氧化物层沉积在字线堆叠的顶部上，第一间隔层和设置在第一间隔层之间的衬底的表面。 从第一间隔层去除氧化物层，从而形成覆盖设置在第一间隔层之间的衬底的表面的剩余氧化物层。 第二间隔层形成在第一间隔层之上，并且覆盖剩余氧化物层的各个部分。 除去剩余的氧化物层，从而形成底切区域。 在形成接触期间，底切区域基本上被接触材料填充。

公开(公告)号：US06218273B1

公开(公告)日：2001-04-17

申请号：US09273868

申请日：1999-03-22

Applicant: Woo-tag Kang

Inventor： Woo-tag Kang

IPC: C30B2518

CPC classification number: H01L21/76224

Abstract: An isolation trench is formed from a first isolation trench in an integrated circuit substrate between active regions in the integrated circuit substrate. An insulating layer is formed in the first isolation trench, wherein the insulating layer includes a portion that protrudes from the first isolation trench. A second isolation trench is formed on the first isolation trench and self-aligned to the active regions in the integrated circuit substrate, wherein the second isolation trench includes the protruding portion of the insulating layer. By forming the isolation trench in two steps, the isolation trench may be formed to the appropriate depth without developing a seam in the insulating layer. In particular, the first isolation trench is formed to a depth and filled with the insulating layer which protrudes from the trench. The second isolation trench is built up around the protruding insulating layer to provide the total depth for adequate isolation of the active areas. The isolation trench may thereby provide improved reliability of the integrated circuit.

Abstract translation: 在集成电路基板中的有源区域之间的集成电路基板中的第一隔离沟槽形成隔离沟槽。 绝缘层形成在第一隔离沟槽中，其中绝缘层包括从第一隔离沟槽突出的部分。 第二隔离沟槽形成在第一隔离沟槽上并与集成电路衬底中的有源区域自对准，其中第二隔离沟槽包括绝缘层的突出部分。 通过在两个步骤中形成隔离沟槽，隔离沟槽可以形成为适当的深度，而不会在绝缘层中形成接缝。 特别地，第一隔离沟槽形成为深度并填充有从沟槽突出的绝缘层。 围绕突出的绝缘层构建第二隔离沟槽，以提供用于充分隔离有源区域的总深度。 因此，隔离沟槽可以提供集成电路的改进的可靠性。