公开(公告)号：US20180069024A1

公开(公告)日：2018-03-08

申请号：US15795454

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Zuoguang LIU ,  Xin MIAO

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76281 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66583 ,  H01L29/7838 ,  H01L29/7842 ,  H01L29/78684

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

公开(公告)号：US09576798B2

公开(公告)日：2017-02-21

申请号：US14934567

申请日：2015-11-06

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Christophe Maleville

IPC: H01L21/8238 ,  H01L27/12 ,  H01L21/266 ,  H01L21/336 ,  H01L21/225 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L21/84 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L21/2253 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/76251 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/32 ,  H01L29/7849

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括提供包括基底基板，在基底基板上方的应变应力层，表面半导体层和应力层与表面半导体层之间的电介质层的绝缘体上半导体 。 离子被注入或穿过应力层的第一区域，并且在应力层的第一区域上方的表面半导体层上形成附加的半导体材料。 在应力层的第一区域上方的表面半导体层的第一区域中的应变状态被改变，并且沟槽结构至少部分地形成到基底衬底中。 在应力层的第二区域上方的表面半导体层的第二区域中改变应变状态。 使用这种方法制造半导体结构。

公开(公告)号：US09570437B2

公开(公告)日：2017-02-14

申请号：US14279605

申请日：2014-05-16

Applicant: NXP B.V.

Inventor： Priscilla Boos ,  Rob van Dalen ,  Erik Spaan

IPC: H01L27/06 ,  H01L21/762 ,  H01L29/06 ,  H01L21/84 ,  H01L29/73 ,  H01L27/12 ,  H01L29/786 ,  H01L29/861 ,  H01L29/40 ,  H01L21/8249 ,  H01L29/739 ,  H01L29/74

CPC classification number: H01L27/0623 ,  H01L21/7621 ,  H01L21/76221 ,  H01L21/76227 ,  H01L21/76281 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7302 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/78624 ,  H01L29/861

Abstract: A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.

Abstract translation: 公开了一种半导体管芯，其包括在衬底的上主表面上的横向半导体器件，所述集成电路包括在衬底上的硅层，在硅层中的凹陷，在凹槽内的LOCOS氧化硅层，并且具有生长 所述上表面与所述硅层的未凹陷部分的表面共面，其中所述凹槽下方的所述硅层具有不均匀的横向掺杂分布，并且包括在所述侧向半导体器件的漂移区域中。 还公开了制造这种裸片的方法，以及集成电路和驱动器电路。

公开(公告)号：US20160225768A1

公开(公告)日：2016-08-04

申请号：US14609507

申请日：2015-01-30

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L27/092 ,  H01L21/8252 ,  H01L29/32 ,  H01L21/02 ,  H01L27/12 ,  H01L29/205

CPC classification number: H01L21/8258 ,  H01L21/76281 ,  H01L27/092 ,  H01L27/1207

Abstract: After forming a first trench and a second trench extending through a top elemental semiconductor layer present on a substrate including, from bottom to top, a handle substrate, a compound semiconductor template layer and a buried insulator layer to define a top elemental semiconductor layer portion for a p-type metal-oxide-semiconductor transistor, the second trench is vertically expanded through the buried insulator layer to provide an expanded second trench that exposes a top surface of the compound semiconductor template layer at a bottom of the expanded second trench. A stack of a compound semiconductor buffer layer and a top compound semiconductor layer is epitaxially grown on the compound semiconductor template layer within the expanded second trench for an n-type metal-oxide-semiconductor transistor.

Abstract translation: 在形成第一沟槽和第二沟槽之后延伸穿过衬底上的顶部元素半导体层，包括从底部到顶部的手柄衬底，化合物半导体模板层和掩埋绝缘体层，以限定顶部元素半导体层部分，用于 p型金属氧化物半导体晶体管，第二沟槽通过掩埋绝缘体层垂直扩展，以提供扩展的第二沟槽，其在扩展的第二沟槽的底部暴露化合物半导体模板层的顶表面。 在用于n型金属氧化物半导体晶体管的扩展的第二沟槽内的化合物半导体模板层上外延生长化合物半导体缓冲层和顶部化合物半导体层的堆叠。

公开(公告)号：US20150194421A1

公开(公告)日：2015-07-09

申请号：US14279605

申请日：2014-05-16

Applicant: NXP B.V.

Inventor： Priscilla Boos ,  Rob van Dalen ,  Erik Spaan

IPC: H01L27/06 ,  H01L29/40 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/0623 ,  H01L21/7621 ,  H01L21/76221 ,  H01L21/76227 ,  H01L21/76281 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/402 ,  H01L29/404 ,  H01L29/7302 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/78624 ,  H01L29/861

Abstract: A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.

Abstract translation: 公开了一种半导体管芯，其包括在衬底的上主表面上的侧向半导体器件，该集成电路包括衬底上的硅层，在硅层中的凹陷，在凹槽内的一层LOCOS氧化硅，并且具有生长 与硅层的未凹陷部分的表面共面的上表面，其中凹陷下方的硅层具有不均匀的横向掺杂分布，并且包括在横向半导体器件的漂移区域中。 还公开了制造这种裸片的方法，集成电路和驱动电路也是如此。

公开(公告)号：US08835278B2

公开(公告)日：2014-09-16

申请号：US13885884

申请日：2011-11-16

Applicant: Gouri Sankar Kar ,  Antonino Cacciato ,  Min-Soo Kim

Inventor： Gouri Sankar Kar ,  Antonino Cacciato ,  Min-Soo Kim

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115

CPC classification number: H01L21/76224 ,  H01L21/76208 ,  H01L21/76281 ,  H01L21/823431 ,  H01L27/11521

Abstract: Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.

Abstract translation: 公开了在用于半导体器件的翅片下面形成局部埋置介质层的方法。 在一些实施例中，该方法可以包括提供包括体半导体材料并在衬底中形成至少两个沟槽的衬底，从而形成至少一个鳍。 该方法还包括用绝缘材料填充沟槽并且部分地去除绝缘材料以在每个沟槽的底部形成绝缘区域。 该方法还包括至少在沟槽的侧壁上沉积衬垫，从每个绝缘区域的顶部去除层，从而在鳍的底部区域形成窗口开口，并且将本体半导体材料 通过窗口打开翅片的底部区域，从而在翅片的底部区域中形成局部埋置的介质层。

公开(公告)号：US20140127878A1

公开(公告)日：2014-05-08

申请号：US13667384

申请日：2012-11-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORP

Inventor： Solomon Assefa ,  William M. Green ,  Marwan H. Khater ,  Yurri A. Vlasov

IPC: H01L21/762

CPC classification number: H01L21/76205 ,  H01L21/0274 ,  H01L21/76232 ,  H01L21/76281 ,  H01L21/76283

Abstract: Photonic devices are created by laterally growing a semiconductor material (i.e., a localized semiconductor-on-insulator layer) over a localized buried oxide (BOX) created in a semiconductor by either a trench isolation process or thermal oxidation. In one embodiment, and after trench formation in a semiconductor substrate, the trench is filled with oxide to create a localized BOX. The top surface of the BOX is recessed to depth below the topmost surface of the semiconductor substrate to expose sidewall surfaces of the semiconductor substrate within each trench. A semiconductor material is then epitaxially grown from the exposed sidewall surfaces of the semiconductor substrate.

Abstract translation: 通过在半导体中通过沟槽隔离工艺或热氧化产生的局部掩埋氧化物（BOX）横向生长半导体材料（即，局部绝缘体上半导体层）来产生光子器件。 在一个实施例中，并且在半导体衬底中形成沟槽之后，沟槽填充有氧化物以产生局部BOX。 BOX的顶表面凹进到半导体衬底的最上表面的深度以暴露在每个沟槽内的半导体衬底的侧壁表面。 然后从半导体衬底的暴露的侧壁表面外延生长半导体材料。

公开(公告)号：US20140065794A1

公开(公告)日：2014-03-06

申请号：US13885884

申请日：2011-11-16

Applicant: Gouri Sankar Kar ,  Antonino Cacciato ,  Min-Soo Kim

Inventor： Gouri Sankar Kar ,  Antonino Cacciato ,  Min-Soo Kim

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76208 ,  H01L21/76281 ,  H01L21/823431 ,  H01L27/11521

Abstract: Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.

Abstract translation: 公开了在用于半导体器件的翅片下面形成局部埋置介质层的方法。 在一些实施例中，该方法可以包括提供包括体半导体材料并在衬底中形成至少两个沟槽的衬底，从而形成至少一个鳍。 该方法还包括用绝缘材料填充沟槽并且部分地去除绝缘材料以在每个沟槽的底部形成绝缘区域。 该方法还包括至少在沟槽的侧壁上沉积衬垫，从每个绝缘区域的顶部去除层，从而在鳍的底部区域形成窗口开口，并且将本体半导体材料 通过窗口打开翅片的底部区域，从而在翅片的底部区域中形成局部埋置的介质层。

公开(公告)号：US20140061862A1

公开(公告)日：2014-03-06

申请号：US13597799

申请日：2012-08-29

Applicant: Reinaldo A. VEGA ,  Michael V. AQUILINO ,  Daniel J. JAEGER

Inventor： Reinaldo A. VEGA ,  Michael V. AQUILINO ,  Daniel J. JAEGER

IPC: H01L29/161 ,  H01L21/20

CPC classification number: H01L21/76281 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/76208 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

Abstract translation: 提供了包括第一外延半导体层的半导体衬底。 第一外延半导体层包括第一半导体材料，并且可以形成在下面的外延衬底层上，或者可以是整个半导体衬底。 包含第二半导体材料的第二外延半导体层外延地形成在第一外延半导体层上。 包括第二单晶半导体材料的部分的半导体翅片通过使用第一外延半导体层作为蚀刻停止层的第二外延半导体层图案化而形成。 至少第一外延半导体层的上部被氧化以提供电绝缘半导体鳍片的局部氧化物层。 第一半导体材料可以从相对于第二半导体材料更容易氧化的材料中选择，以在形成局部氧化物层之后为半导体翅片提供均匀的高度。

公开(公告)号：US08664746B2

公开(公告)日：2014-03-04

申请号：US13237671

申请日：2011-09-20

Applicant: Janusz Karol Korycinski ,  Wanliang Wen

Inventor： Janusz Karol Korycinski ,  Wanliang Wen

IPC: H01L29/30

CPC classification number: H01L21/3226 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/1203 ,  H01L29/32 ,  H01L29/78

Abstract: A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps.

Abstract translation: 提供了一种绝缘硅（SOI）晶圆。 在晶片的有源硅衬底上形成电介质层。 对电介质层进行图案化和蚀刻以暴露硅衬底的选定部分。 然后将杂质引入硅衬底的暴露部分中以用作吸杂区域。 然后去除电介质层，并在硅衬底上生长外延硅层。 通过吸气区域在硅的外延层中蚀刻沟槽，部分地去除吸气区域和其中包含的任何污染物。 吸附区域的剩余部分在后续工艺步骤中仍然作为吸气区域。