Fixed mobile convergence terminal using downloadable wideband voice codec, method thereof and method of providing wideband voice codec in call control server
    2.
    发明授权
    Fixed mobile convergence terminal using downloadable wideband voice codec, method thereof and method of providing wideband voice codec in call control server 有权
    使用可下载的宽带语音编解码器的固定移动融合终端,其方法和在呼叫控制服务器中提供宽带语音编解码的方法

    公开(公告)号:US08611951B2

    公开(公告)日:2013-12-17

    申请号:US12899041

    申请日:2010-10-06

    IPC分类号: H04M1/00 H04L12/28

    摘要: A fixed mobile convergence terminal using a wideband voice codec is provided. The fixed mobile convergence terminal includes a communication unit configured to connect to a network, and a control unit configured to download a wideband voice codec identical to a wideband voice codec of an opposite party terminal from a call control server in a call setting with the opposite party terminal through the communication unit, so that a high-quality voice call function is achieved.

    摘要翻译: 提供了一种使用宽带语音编解码器的固定移动融合终端。 固定移动会聚终端包括被配置为连接到网络的通信单元,以及控制单元,被配置为在具有相反的呼叫设置中从呼叫控制服务器下载与对方终端的宽带语音编解码器相同的宽带语音编解码器 通过通信单元,实现高质量的语音通话功能。

    APPARATUS AND METHOD FOR MEASURING VOICE QUALITY OF VoIP TERMINAL USING WIDEBAND VOICE CODEC
    3.
    发明申请
    APPARATUS AND METHOD FOR MEASURING VOICE QUALITY OF VoIP TERMINAL USING WIDEBAND VOICE CODEC 审中-公开
    使用宽带语音编解码器测量VoIP终端语音质量的装置和方法

    公开(公告)号:US20120163214A1

    公开(公告)日:2012-06-28

    申请号:US13333502

    申请日:2011-12-21

    IPC分类号: H04W24/00

    摘要: A method for measuring voice quality in a wireless communication network includes measuring an MOS of a signal using a narrowband voice codec and an MOS of a signal using a wideband voice codec in a cable loopback environment, calculating a wideband voice codec correction coefficient using the measured MOS, measuring an MOS of a signal using the narrowband voice codec and an MOS of a signal using the wideband voice codec in a terminal connection environment; and outputting a value obtained by adding the wideband voice codec correction coefficient to the measured MOS in the terminal connection environment.

    摘要翻译: 一种用于测量无线通信网络中的语音质量的方法包括:在电缆环回环境中使用窄带语音编解码器和使用宽带语音编解码器的信号的MOS测量信号的MOS,使用所测量的宽带语音编解码器校正系数 MOS,在终端连接环境中使用窄带语音编解码器测量信号的MOS信号和使用宽带语音编解码器的信号的MOS; 并且在终端连接环境中输出通过将宽带语音编解码器校正系数与所测量的MOS相加而获得的值。

    INTERNET PHONE TERMINAL USING WIDEBAND VOICE CODEC AND COMMUNICATION METHOD FOR INTERNET PHONE
    4.
    发明申请
    INTERNET PHONE TERMINAL USING WIDEBAND VOICE CODEC AND COMMUNICATION METHOD FOR INTERNET PHONE 审中-公开
    互联网电话终端使用宽带语音编解码器和互联网通信方式

    公开(公告)号:US20100272097A1

    公开(公告)日:2010-10-28

    申请号:US12745905

    申请日:2008-06-26

    IPC分类号: H04L12/66

    CPC分类号: H04L12/66

    摘要: Provided are an Internet phone terminal that applies a wideband voice codec, and an Internet phone communication method. A wideband voice signal received from the Internet through a wired line or wirelessly is decoded using the wideband voice codec, and a wideband voice signal received through a microphone supporting a wideband is encoded using the wideband voice codec, so that the Internet phone terminal can provide high quality voice communication.

    摘要翻译: 提供了应用宽带语音编解码器的互联网电话终端和互联网电话通信方法。 从因特网通过有线线路或无线地接收的宽带语音信号使用宽带语音编解码器进行解码,并且通过使用宽带语音编解码器对支持宽带的麦克风接收的宽带语音信号进行编码,使得因特网电话终端可以提供 高品质的语音通信。

    Apparatus for developing and verifying system-on-chip for internet phone
    5.
    发明授权
    Apparatus for developing and verifying system-on-chip for internet phone 有权
    用于互联网电话开发和验证片上系统的设备

    公开(公告)号:US07526679B2

    公开(公告)日:2009-04-28

    申请号:US11183673

    申请日:2005-07-18

    IPC分类号: G06F11/00

    CPC分类号: G06F11/267

    摘要: Provided is an apparatus for developing and verifying a system-on-chip for an Internet phone. The object of the present invention is to provide the system-on-chip developing and verifying apparatus for the Internet phone, which can develop and verify the system-on-chip simultaneously by integrating an Advanced RISC Machine(ARM) core module, a field programmable gate array (FPGA), a peripheral interface and the system-on-chip. The apparatus includes an ARM core module performing a core processor function, a peripheral interface including a memory and many external input/output devices, a FPGA controlling the ARM core module and performing a control function for connecting the ARM core module and the peripheral interface, and a system-on-chip integrating the functions of the ARM core module and the FPGA.

    摘要翻译: 提供了一种用于开发和验证因特网电话的片上系统的装置。 本发明的目的是提供一种用于互联网电话的系统级芯片开发和验证装置,其可以通过集成高级RISC机(ARM)核心模块,现场 可编程门阵列(FPGA),外围接口和片上系统。 该装置包括执行核心处理器功能的ARM核心模块,包括存储器和许多外部输入/输出设备的外围接口,控制ARM核心模块的FPGA并执行用于连接ARM核心模块和外围接口的控制功能, 以及集成ARM内核模块和FPGA功能的片上系统。

    Communication terminal for wire and wireless internet phone
    6.
    发明授权
    Communication terminal for wire and wireless internet phone 失效
    有线和无线网络电话通信终端

    公开(公告)号:US07522583B2

    公开(公告)日:2009-04-21

    申请号:US10414933

    申请日:2003-04-16

    摘要: Disclosed is a communication terminal for a wire and wireless network phone which comprises: a communication service controller, including a RISC processor, for processing protocols that satisfy respective communication interfaces in hardware and software manners; a reset unit for applying a reset signal to be used for the communication service controller; a clock signal unit for supplying clock signals needed for the communication service controller; a memory connected to the communication service controller, for storing a start program, a terminal management program, user data, and various application programs; and an access unit for providing a VoIP telephone function, a DSL access function, an analog telephone function, an Ethernet access function, a wireless network access function, and an EIA232 access function.

    摘要翻译: 公开了一种有线和无线网络电话的通信终端,其包括:包括RISC处理器的通信服务控制器,用于以硬件和软件方式处理满足相应通信接口的协议; 复位单元,用于施加要用于所述通信服务控制器的复位信号; 时钟信号单元,用于提供通信服务控制器所需的时钟信号; 连接到通信服务控制器的存储器,用于存储起始程序,终端管理程序,用户数据和各种应用程序; 以及用于提供VoIP电话功能,DSL接入功能,模拟电话功能,以太网接入功能,无线网络接入功能和EIA232接入功能的接入单元。

    Apparatus for developing and verifying system-on-chip for internet phone

    公开(公告)号:US20060143526A1

    公开(公告)日:2006-06-29

    申请号:US11183673

    申请日:2005-07-18

    IPC分类号: G06F11/00

    CPC分类号: G06F11/267

    摘要: Provided is an apparatus for developing and verifying a system-on-chip for an Internet phone. The object of the present invention is to provide the system-on-chip developing and verifying apparatus for the Internet phone, which can develop and verify the system-on-chip simultaneously by integrating an Advanced RISC Machine(ARM) core module, a field programmable gate array (FPGA), a peripheral interface and the system-on-chip. The apparatus includes an ARM core module performing a core processor function, a peripheral interface including a memory and many external input/output devices, a FPGA controlling the ARM core module and performing a control function for connecting the ARM core module and the peripheral interface, and a system-on-chip integrating the functions of the ARM core module and the FPGA.

    System-on-chip development apparatus for wire and wireless internet phone
    8.
    发明申请
    System-on-chip development apparatus for wire and wireless internet phone 有权
    有线和无线网络电话系统级片上开发设备

    公开(公告)号:US20050138582A1

    公开(公告)日:2005-06-23

    申请号:US10856278

    申请日:2004-05-28

    IPC分类号: H04L12/66 G06F17/50

    CPC分类号: G06F17/5022

    摘要: The present invention is directed to a system-on-chip development apparatus for wire/wireless Internet telephone. The system-on-chip development apparatus for wire/wireless Internet telephone according to the present invention adds functions indispensable to a RISC core, constructs a core kernel section using a device integrating additional FPGAs available to support additional functions, and provides a plurality of interfaces necessary to an Internet telephone function centering around the core kernel section. With this, the number of necessary component parts can be minimized to facilitate design and simplify the configuration thereof.

    摘要翻译: 本发明涉及一种用于有线/无线因特网电话的片上系统开发装置。 根据本发明的用于有线/无线因特网电话的系统级芯片开发装置增加了对RISC核心不可或缺的功能,使用集成可用于支持附加功能的附加FPGA的设备来构建核心内核部分,并提供多个接口 以核心核心部分为中心的互联网电话功能是必需的。 由此,可以将所需的部件的数量最小化,以便于设计并简化其构造。

    System-on-chip development apparatus for wire and wireless internet phone
    9.
    发明授权
    System-on-chip development apparatus for wire and wireless internet phone 有权
    有线和无线网络电话系统级片上开发设备

    公开(公告)号:US07296186B2

    公开(公告)日:2007-11-13

    申请号:US10856278

    申请日:2004-05-28

    IPC分类号: G06F11/00

    CPC分类号: G06F17/5022

    摘要: The present invention is directed to a system-on-chip development apparatus for wire/wireless Internet telephone. The system-on-chip development apparatus for wire/wireless Internet telephone according to the present invention adds functions indispensable to a RISC core, constructs a core kernel section using a device integrating additional FPGAs available to support additional functions, and provides a plurality of interfaces necessary to an Internet telephone function centering around the core kernel section. With this, the number of necessary component parts can be minimized to facilitate design and simplify the configuration thereof.

    摘要翻译: 本发明涉及一种用于有线/无线因特网电话的片上系统开发装置。 根据本发明的用于有线/无线因特网电话的系统级芯片开发装置增加了对RISC核心不可或缺的功能,使用集成可用于支持附加功能的附加FPGA的设备来构建核心内核部分,并提供多个接口 以核心核心部分为中心的互联网电话功能是必需的。 由此,可以将所需的部件的数量最小化,以便于设计并简化其构造。

    Dual port random access memory matching circuit for versa module Europe
bus (VMEbus)
    10.
    发明授权
    Dual port random access memory matching circuit for versa module Europe bus (VMEbus) 失效
    双端口随机存取存储器匹配电路,用于反模块欧洲总线(VMEbus)

    公开(公告)号:US5822769A

    公开(公告)日:1998-10-13

    申请号:US742894

    申请日:1996-11-01

    IPC分类号: G06F13/40 G06F13/00 G06F12/00

    CPC分类号: G06F13/4059

    摘要: A dual port random access memory (RAM) matching circuit for a Versa Module Europe bus (VMEbus) which makes it possible to have a higher capacity when transmitting and receiving data by using a RAM which is possible to bidirectionally access during a communication between processors using a VMEbus of an electronic switching system. The dual port RAM matching circuit includes a dual port RAM for bidirectionally outputting/inputting a data in accordance with an address and a control signal, an address matching unit for selecting first through sixteenth addresses from a local system or first through sixteenth addresses from a VMEbus in accordance with the control signal, and a data matching unit for selecting 0-th through thirty first CPU data or 0-th through thirty first VMEbus data from the local system in accordance with the control signal from the control bus, and for checking a parity during a data transmission and receiving operation. The dual port RAM matching circuit further includes a control signal matching unit for selecting either the control signal from the local system or the control signal from the VMEbus in accordance with the control signal from the control bus and for outputting the selected control signal to the control bus, and a control signal generator for receiving an address information signal and a clock signal from the local system, and an address information signal from the VMEbus, and outputting control signals to the control bus.

    摘要翻译: 一种用于Versa模块欧洲总线(VMEbus)的双端口随机存取存储器(RAM)匹配电路,使得可以通过使用RAM进行发送和接收数据时具有更高的容量,RAM可以在处理器之间的通信期间双向访问 电子交换系统的VMEbus。 双端口RAM匹配电路包括用于根据地址和控制信号双向输出/输入数据的双端口RAM,用于从本地系统中选择第一至第十六地址的地址匹配单元或从VME总线 根据控制信号,以及数据匹配单元,用于根据来自控制总线的控制信号从本地系统中选择0到30个第一CPU数据或第0到第30个第一VME总线数据,并且用于检查 在数据发送和接收操作期间的奇偶校验。 双端口RAM匹配电路还包括控制信号匹配单元,用于根据来自控制总线的控制信号选择来自本地系统的控制信号或来自VME总线的控制信号,并将所选择的控制信号输出到控制 总线和控制信号发生器,用于从本地系统接收地址信息信号和时钟信号,以及来自VMEbus的地址信息信号,并将控制信号输出到控制总线。