公开(公告)号：US07116130B2

公开(公告)日：2006-10-03

申请号：US10742663

申请日：2003-12-18

Applicant: Fang-Bin Liu ,  Wu-Han Yang

Inventor： Fang-Bin Liu ,  Wu-Han Yang

IPC: G06F7/38 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177 ,  H03K17/693

CPC classification number: G06F17/5054

Abstract: A method for effectively re-downloading data to a Field Programmable Gate Array (FPGA). The method uses two Complex Programmable Logic Devices (CPLDs) to implement control functions of Write-to-Non-Volatile Random Access Memory (NVRAM) and Write-to-FPGA respectively, in conjunction with a set of connectors with a detection circuit, such that according to a detection state output by the detection circuit to one CPLD implemented with Write-to-FPGA control function, a write-to-NVRAM operation for data is determined if the detection state is logic low and conversely data is written from the NVRAM to the FPGA.

Abstract translation: 一种有效地将数据重新下载到现场可编程门阵列（FPGA）的方法。 该方法使用两个复杂可编程逻辑器件（CPLD）分别实现写入非易失性随机存取存储器（NVRAM）和写入到FPGA的控制功能，以及一组具有检测电路的连接器，如 根据由检测电路输出的检测状态，通过写到FPGA控制功能实现的一个CPLD，如果检测状态为逻辑低，并且相反地从NVRAM写入数据，则确定数据的写NVR操作 到FPGA。

公开(公告)号：US07210052B2

公开(公告)日：2007-04-24

申请号：US10756879

申请日：2004-01-13

Applicant: De-Wei Lee ,  Wu-Han Yang

Inventor： De-Wei Lee ,  Wu-Han Yang

IPC: G06F1/00 ,  G06F1/12 ,  H04L7/00

CPC classification number: G06F1/12 ,  H04L7/0012 ,  H04L7/0037

Abstract: A method and system for clock synchronization of semiconductor devices. The method uses a master-slave configuration to designate a semiconductor device with the lowest rate clock source as a master device and zero all clock sources inside the semiconductor device in order to output the zeroing lowest rate clock source to slave devices for clock synchronization of all clock sources respectively in the slave devices, and further implements a phase checker in each semiconductor device to ensure clock synchronization inside and between the semiconductor devices, so required clock signals are precisely provided to next internal circuits of the semiconductor devices.

Abstract translation: 一种用于半导体器件时钟同步的方法和系统。 该方法使用主从配置来指定具有最低速率时钟源的半导体器件作为主器件，并且将半导体器件内部的所有时钟源置零，以便将归零最低速率时钟源输出到从器件以用于所有的时钟同步 时钟源，并且还在每个半导体器件中实现相位检查器，以确保半导体器件内部和之间的时钟同步，因此需要将时钟信号精确地提供给半导体器件的下一个内部电路。

公开(公告)号：US07324579B2

公开(公告)日：2008-01-29

申请号：US10764573

申请日：2004-01-27

Applicant: Wu-Han Yang

Inventor： Wu-Han Yang

IPC: H04L27/30

CPC classification number: H04B1/7115 ,  H04B1/7117 ,  H04B2201/7071

Abstract: The present invention is related to a flexible distribution architecture and method for rake receiver of communication system, comprising: a plurality of processing units, further, each processing unit comprises: a plurality of rake receivers, wherein each rake receiver can receive a multi-path signal from its environment and, through a recovery process, outputs a recovered signal therefrom; an combiner, which connects with the plurality of rake receivers and receives a plurality of recovered signals, then further integrates the plural recovered signals which are originated from a same source by an integration process and, consequently, outputs an integrated signal therefrom; a master processing unit, which connects with the plural processing units and, through detecting the signal received, assigns an appropriate number of rake receivers to receive signals, and further the plural integrated signals originated from a same source are integrated by an integration process and, consequently, outputs a compound signal therefrom. The aforementioned rake receivers can be subordinated to different processing units. The present invention further provides a flexible distribution method for rake receivers that are subordinate to different processing units.

Abstract translation: 本发明涉及一种用于通信系统的耙式接收机的灵活分布架构和方法，包括：多个处理单元，每个处理单元包括：多个耙式接收机，其中每个耙式接收机可以接收多路径 来自其环境的信号，并且通过恢复过程从其输出恢复的信号; 组合器，其与多个前置接收器连接并接收多个恢复信号，然后通过积分处理将来自相同源的多个恢复信号进一步积分，并因此从其输出积分信号; 主处理单元，其与多个处理单元连接，并且通过检测接收到的信号，分配适当数量的耙式接收器来接收信号，并且进一步地，通过积分处理将来自相同源的多个积分信号进行积分， 从而输出复合信号。 上述耙式接收器可以从属于不同的处理单元。 本发明还提供了一种用于从属于不同处理单元的耙式接收机的灵活分配方法。

公开(公告)号：US07447524B2

公开(公告)日：2008-11-04

申请号：US11073002

申请日：2005-03-04

Applicant: Wu-Han Yang

Inventor： Wu-Han Yang

IPC: H04B1/38 ,  G06F1/00

CPC classification number: H04J3/0685 ,  H04W28/06 ,  H04W88/08

Abstract: A method and system of cell timing distribution which greatly reduces the bus bandwidth required for transmission of cell timing information in a WCDMA base station. The system of the present invention comprises a timing control unit connected to several communication cells through transmission lines. Each communication cell comprises a timing generator which determines a local timing (sfn) according to a frame boundary signal and a timing difference (t_cell) parameter received from the timing control unit. The frame boundary signal indicates the starting boundary of the central base station (nodeB) timing, whereas the t_cell parameter represents the offset between the local cell timing and the nodeB timing. The timing generator is implemented using a finite state machine and a counter.

Abstract translation: 一种小区定时分配的方法和系统，其大大降低了在WCDMA基站中传输小区定时信息所需的总线带宽。 本发明的系统包括通过传输线连接到多个通信小区的定时控制单元。 每个通信小区包括定时发生器，其根据帧边界信号和从定时控制单元接收的定时差（t_cell）参数确定本地定时（sfn）。 帧边界信号指示中央基站（nodeB）定时的起始边界，而t_cell参数表示本地小区定时与节点B定时之间的偏移。 定时发生器使用有限状态机和计数器实现。

公开(公告)号：US20050197128A1

公开(公告)日：2005-09-08

申请号：US11073002

申请日：2005-03-04

Applicant: Wu-Han Yang

Inventor： Wu-Han Yang

IPC: H04W28/06 ,  H04W88/08 ,  H04Q7/20

CPC classification number: H04J3/0685 ,  H04W28/06 ,  H04W88/08

Abstract: A method and system of cell timing distribution which greatly reduces the bus bandwidth required for transmission of cell timing information in a WCDMA base station. The system of the present invention comprises a timing control unit connected to several communication cells through transmission lines. Each communication cell comprises a timing generator which determines a local timing (sfn) according to a frame boundary signal and a timing difference (t_cell) parameter received from the timing control unit. The frame boundary signal indicates the starting boundary of the central base station (nodeB) timing, whereas the t_cell parameter represents the offset between the local cell timing and the nodeB timing. The timing generator is implemented using a finite state machine and a counter.

Abstract translation: 一种小区定时分配的方法和系统，其大大降低了在WCDMA基站中传输小区定时信息所需的总线带宽。 本发明的系统包括通过传输线连接到多个通信小区的定时控制单元。 每个通信小区包括定时发生器，其根据帧边界信号和从定时控制单元接收的定时差（t_cell）参数确定本地定时（sfn）。 帧边界信号指示中央基站（nodeB）定时的起始边界，而t_cell参数表示本地小区定时与节点B定时之间的偏移。 定时发生器使用有限状态机和计数器实现。