公开(公告)号：US07906426B2

公开(公告)日：2011-03-15

申请号：US11788969

申请日：2007-04-23

申请人： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

发明人： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138

摘要： An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.

摘要翻译： 互连堆叠及其制造方法，其中互连具有垂直侧壁通孔。 互连堆叠包括衬底，形成在衬底中的金属互连，形成在衬底上的蚀刻阻挡层和金属互连，以及层间电介质（ILD）层，其具有形成在其中的至少一个通孔，其延伸穿过形成在衬底上的过渡层 蚀刻停止层。 通过将ILD蚀刻到第一深度并且使互连堆叠灰化以修改通过蚀刻形成的通路的部分与过渡层之间的ILD的一部分而形成通孔。 灰化将ILD的这部分转化为氧化物材料。 该方法包括湿蚀刻互连以去除氧化物材料和过渡层的一部分，以形成延伸穿过ILD到蚀刻停止层的通孔。

公开(公告)号：US20080258308A1

公开(公告)日：2008-10-23

申请号：US11788969

申请日：2007-04-23

申请人： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

发明人： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

IPC分类号： H01L21/4763 ,  H01L21/76 ,  H01L29/40

CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138

摘要： An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.

摘要翻译： 互连堆叠及其制造方法，其中互连具有垂直侧壁通孔。 互连堆叠包括衬底，形成在衬底中的金属互连，形成在衬底上的蚀刻阻挡层和金属互连，以及层间电介质（ILD）层，其具有形成在其中的至少一个通孔，其延伸穿过形成在衬底上的过渡层 蚀刻停止层。 通过将ILD蚀刻到第一深度并且使互连堆叠灰化以修改通过蚀刻形成的通路的部分与过渡层之间的ILD的一部分而形成通孔。 灰化将ILD的这部分转化为氧化物材料。 该方法包括湿蚀刻互连以去除氧化物材料和过渡层的一部分，以形成延伸穿过ILD到蚀刻停止层的通孔。

公开(公告)号：US07749894B2

公开(公告)日：2010-07-06

申请号：US11558342

申请日：2006-11-09

申请人： Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

发明人： Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76835 ,  H01L21/76829 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielectric layer over the low-K dielectric layer, forming an opening through the ultra low-K dielectric layer and the low-K dielectric layer to the interconnect layer, depositing an interconnect metal in the opening, and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

摘要翻译： 提供一种集成电路处理系统，包括提供具有集成电路的衬底，在集成电路上形成互连层，在互连层上施加低K电介质层，在低K电介质层上施加超低K电介质层 电介质层，通过超低K电介质层和低K电介质层形成开口到互连层，在开口中沉积互连金属，并对互连金属和超低K电介质层进行化学机械抛光 。

公开(公告)号：US20080111238A1

公开(公告)日：2008-05-15

申请号：US11558342

申请日：2006-11-09

申请人： Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

发明人： Xianbin Wang ,  Juan Boon Tan ,  Liang-Choo Hsia ,  Teck Jung Tang ,  Huang Liu

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76835 ,  H01L21/76829 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielectric layer over the low-K dielectric layer, forming an opening through the ultra low-K dielectric layer and the low-K dielectric layer to the interconnect layer, depositing an interconnect metal in the opening, and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

摘要翻译： 提供一种集成电路处理系统，包括提供具有集成电路的衬底，在集成电路上形成互连层，在互连层上施加低K电介质层，在低K电介质层上施加超低K电介质层 电介质层，通过超低K电介质层和低K电介质层形成开口到互连层，在开口中沉积互连金属，并对互连金属和超低K电介质层进行化学机械抛光 。

公开(公告)号：US08637993B2

公开(公告)日：2014-01-28

申请号：US13453043

申请日：2012-04-23

申请人： Chun Yu Wong ,  Ramakanth Alapati ,  Teck Jung Tang

发明人： Chun Yu Wong ,  Ramakanth Alapati ,  Teck Jung Tang

IPC分类号： H01L23/48 ,  H01L29/10 ,  H01L23/52

CPC分类号： H01L21/76816 ,  H01L21/76898 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.

摘要翻译： 形成集成电路器件的方法包括提供包括有源器件的衬底，在衬底中形成通孔硅，形成与有源器件的器件接触，在穿过硅通孔和器件触点上形成导电层，以及 形成用于将导电层与穿通硅通孔电连接的连接通孔结构。 集成电路器件包括形成衬底硅材料的通硅通孔，形成在穿通硅通孔上的导电层，以及形成在导电层和通硅通孔之间的连接通路结构，用于将导电层与通孔 硅通孔。 连接通孔结构包括与第二系列通孔杆相交的第一系列通孔条。

公开(公告)号：US20130277854A1

公开(公告)日：2013-10-24

申请号：US13453043

申请日：2012-04-23

申请人： Chun Yu Wong ,  Ramakanth Alapati ,  Teck Jung Tang

发明人： Chun Yu Wong ,  Ramakanth Alapati ,  Teck Jung Tang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76816 ,  H01L21/76898 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.

摘要翻译： 形成集成电路器件的方法包括提供包括有源器件的衬底，在衬底中形成通孔硅，形成与有源器件的器件接触，在穿过硅通孔和器件触点上形成导电层，以及 形成用于将导电层与穿通硅通孔电连接的连接通孔结构。 集成电路器件包括形成衬底硅材料的通硅通孔，形成在穿通硅通孔上的导电层，以及形成在导电层和通硅通孔之间的连接通路结构，用于将导电层与通孔 硅通孔。 连接通孔结构包括与第二系列通孔杆相交的第一系列通孔条。

公开(公告)号：US08283193B2

公开(公告)日：2012-10-09

申请号：US12541373

申请日：2009-08-14

申请人： Soon Yoeng Tan ,  Teck Jung Tang

发明人： Soon Yoeng Tan ,  Teck Jung Tang

IPC分类号： H01L21/00

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacture an integrated circuit system includes: forming an insulation region in a base layer; filling an insulator in the insulation region around a perimeter of a main chip region; forming a contact directly on and within planar extents of the insulator; and forming an upper layer over the contact to protect the main chip region.

摘要翻译： 一种集成电路系统的制造方法，包括：在基底层中形成绝缘区域; 在主芯片区域的周边周围的绝缘区域填充绝缘体; 直接在绝缘体的平面范围内形成触点; 并在接触件上形成上层以保护主芯片区域。

公开(公告)号：US09069923B2

公开(公告)日：2015-06-30

申请号：US13161514

申请日：2011-06-16

申请人： Soon Yoeng Tan ,  Teck Jung Tang ,  Ian D. Melville ,  Yelei Vianna Yao ,  Yasushi Yamagata

发明人： Soon Yoeng Tan ,  Teck Jung Tang ,  Ian D. Melville ,  Yelei Vianna Yao ,  Yasushi Yamagata

IPC分类号： G06F17/50 ,  G06F7/06 ,  G06F1/00 ,  H01L29/66

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  G06F2217/66 ,  H01L22/32

摘要： Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.

摘要翻译： 多项目晶片包括来自不同IP所有者的多个小芯片。 采用知识产权保护措施实施不相关的小白鼠，以防止非相关知识产权拥有者的知识产权披露。

公开(公告)号：US20110037140A1

公开(公告)日：2011-02-17

申请号：US12541373

申请日：2009-08-14

申请人： Soon Yoeng Tan ,  Teck Jung Tang

发明人： Soon Yoeng Tan ,  Teck Jung Tang

IPC分类号： H01L29/06 ,  H01L21/768 ,  H01L21/762

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacture an integrated circuit system includes: forming an insulation region in a base layer; filling an insulator in the insulation region around a perimeter of a main chip region; forming a contact directly on and within planar extents of the insulator; and forming an upper layer over the contact to protect the main chip region.

摘要翻译： 一种集成电路系统的制造方法，包括：在基底层中形成绝缘区域; 在主芯片区域的周边周围的绝缘区域填充绝缘体; 直接在绝缘体的平面范围内形成触点; 并在接触件上形成上层以保护主芯片区域。