公开(公告)号：US20240176943A1

公开(公告)日：2024-05-30

申请号：US18235437

申请日：2023-08-18

Applicant: X DEVELOPMENT LLC

Inventor： Xiaoqing Xu ,  Herman Schmit ,  Alessandro Tempia Calvino

IPC: G06F30/398 ,  G06F30/31

CPC classification number: G06F30/398 ,  G06F30/31

Abstract: The technology involves the auto-creation of custom standard cells. The process may include receiving specifications for implementing a set of functionalities in an integrated circuit to be fabricated. From this, the system identifies which cells are required to implement the set of functionalities. The identified cells are evaluated against a standard cell library stored in memory to determine which of the cells are not in the standard cell library. The system automatically creates the cells that are not in the standard cell library. The system can then utilize the automatically created cells to fabricate the integrated circuit. Benefits of such an approach include reduced design, development time and improved design quality of results. The resulting new cells may have fewer transistors, less area/power and improved performance than a standard cell from a preexisting library, especially since such standard cells would not necessarily be configurable to perform the desired functions.

公开(公告)号：US20240169134A1

公开(公告)日：2024-05-23

申请号：US18462628

申请日：2023-09-07

Applicant: X DEVELOPMENT LLC

Inventor： Alessandro Tempia Calvino ,  Xiaoqing Xu ,  Herman Schmit

IPC: G06F30/327 ,  G06F17/11 ,  G06F30/337

CPC classification number: G06F30/327 ,  G06F17/11 ,  G06F30/337

Abstract: The technology involves transistor-level synthesis for integrated circuit design and fabrication. According to one aspect, a computer-implemented method performs transistor-level synthesis for an integrated circuit element. This includes generating single-stage transistor networks from Boolean functions, in which each single-stage transistor network is composed of a pulldown network and a pullup network. The single-stage transistor networks are scaled to multi-stage transistor networks to globally optimize for factored form literals. Technology mapping can then be performed based on the factored form literals to generate a circuit design.