公开(公告)号：US12019526B2

公开(公告)日：2024-06-25

申请号：US17746843

申请日：2022-05-17

Applicant: XILINX, INC.

Inventor： David Tran ,  Aditi R. Ganesan ,  Anurag Goyal

IPC: H03L7/081 ,  G06F11/16

CPC classification number: G06F11/1679 ,  H03L7/0814

Abstract: Methods and systems to detect a metastable condition and suppress/mask a signal during the metastable condition. The metastable condition may arise from asynchronous sampling. Techniques disclosed herein may be configured to enable asynchronous lock-stepping, where outputs of redundant circuit blocks of a first clock domain are received at input nodes of a second clock domain. In the second clock domain, logic states at the input nodes are compared to detect errors, and results of the comparison are masked during transitions at the input nodes. Masking may be constrained to situations where logic states at the input nodes differ.