公开(公告)号：US12019526B2

公开(公告)日：2024-06-25

申请号：US17746843

申请日：2022-05-17

Applicant: XILINX, INC.

Inventor： David Tran ,  Aditi R. Ganesan ,  Anurag Goyal

IPC: H03L7/081 ,  G06F11/16

CPC classification number: G06F11/1679 ,  H03L7/0814

Abstract: Methods and systems to detect a metastable condition and suppress/mask a signal during the metastable condition. The metastable condition may arise from asynchronous sampling. Techniques disclosed herein may be configured to enable asynchronous lock-stepping, where outputs of redundant circuit blocks of a first clock domain are received at input nodes of a second clock domain. In the second clock domain, logic states at the input nodes are compared to detect errors, and results of the comparison are masked during transitions at the input nodes. Masking may be constrained to situations where logic states at the input nodes differ.

公开(公告)号：US11327836B1

公开(公告)日：2022-05-10

申请号：US17037382

申请日：2020-09-29

Applicant: XILINX, INC.

Inventor： Danny Tsung-Heng Wu ,  David Tran

IPC: G06F11/00 ,  G06F11/10

Abstract: Some examples herein provide for protection of data on a data path in a memory system in an integrated circuit. In an example, an integrated circuit includes a bit checker circuit, an Error Correcting Code (ECC) encoder circuit, an ECC decoder circuit, and a check bit generation circuit. The bit checker circuit is configured to check write data based on write-path check bit(s). The ECC encoder circuit is configured to generate a write encoded ECC value based on the write data. The write encoded ECC value is to be written to the memory with the write data. The ECC decoder circuit is configured to decode a read encoded ECC value and check read data based on the read encoded ECC value. The read encoded ECC value and read data are read from the memory. The check bit generation circuit is configured to generate read-path check bit(s) from the read data.