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公开(公告)号:US20220283985A1
公开(公告)日:2022-09-08
申请号:US17826070
申请日:2022-05-26
Applicant: XILINX, INC.
Inventor: Goran Hk BILSKI , Juan J. NOGUERA SERRA , Baris OZGUL , Jan LANGER , David CLARKE , Sneha Bhalchandra DATE
IPC: G06F15/80 , G06F13/40 , G06F15/173 , G06F13/16
Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.
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公开(公告)号:US20220015588A1
公开(公告)日:2022-01-20
申请号:US17468346
申请日:2021-09-07
Applicant: XILINX, INC.
Inventor: Peter MCCOLGAN , Goran Hk BILSKI , Juan J. NOGUERA SERRA , Jan LANGER , Baris OZGUL , David CLARKE
Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.
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