公开(公告)号：US20220015588A1

公开(公告)日：2022-01-20

申请号：US17468346

申请日：2021-09-07

Applicant: XILINX, INC.

Inventor： Peter MCCOLGAN ,  Goran Hk BILSKI ,  Juan J. NOGUERA SERRA ,  Jan LANGER ,  Baris OZGUL ,  David CLARKE

IPC: A47K11/02 ,  E04H1/12 ,  E04H15/38

Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.

公开(公告)号：US20230059970A1

公开(公告)日：2023-02-23

申请号：US17867630

申请日：2022-07-18

Applicant: XILINX, INC.

Inventor： Francisco Barat QUESADA ,  Baris OZGUL ,  Dylan STUART ,  Stephan MUNZ ,  Zachary DICKMAN ,  Javier CABEZAS RODRIGUEZ ,  David Patrick CLARKE ,  Pedro Miguel Parola DUARTE ,  Peter MCCOLGAN ,  Juan J. NOGUERA SERRA

IPC: G06N20/00

Abstract: Examples herein describe techniques for reducing the amount of memory used during weight sparsity. When decompressing the weights, the uncompressed weight data typically has many zero values. By knowing the location of these zero values (e.g., their indices in a weight matrix), the processor core can prune some of the activations (e.g., logically reduce the size of the activation matrix) which improves the efficiency of the processor core. In embodiments herein, the processor core includes logic for identifying the indices of the non-zero value after decompressing the compressed weights. These indices can then be used to prune the activations to improve the efficiency of the processor core.