公开(公告)号：US12231532B1

公开(公告)日：2025-02-18

申请号：US16831356

申请日：2020-03-26

Applicant: XILINX, INC.

Inventor： Devanjan Maiti ,  Robert Bellarmin Susai ,  Jayaram Pvss

IPC: H04L9/06 ,  G06F9/30 ,  G06F13/28 ,  H04L9/08

Abstract: Examples herein describe a scalable tweak engine and prefetching tweak values. Regarding the scalable tweak engine, it can be designed to accommodate different bus widths of data. The scalable tweak engine described herein includes multiple tweak calculators that can be daisy chained together to output multiple tweak values every clock cycle. These tweak values can be sent to multiple encryption cores so that multiple data blocks can be encrypted in parallel. Regarding prefetching tweak values, previous encryption engines incur a delay as the tweak value (e.g., a metadata value) for a data block is calculated. In the embodiments herein, the encryption engine can include an independent metadata engine that determines the metadata value for a subsequent data block while the current data block is being encrypted.

公开(公告)号：US11689361B1

公开(公告)日：2023-06-27

申请号：US17093353

申请日：2020-11-09

Applicant: Xilinx, Inc.

Inventor： Devanjan Maiti ,  Robert Bellarmin Susai ,  Jayaram Pvss

IPC: H04L9/06 ,  H04L9/08 ,  H03K19/21 ,  H04L9/34

CPC classification number: H04L9/0861 ,  H03K19/21 ,  H04L9/0631 ,  H04L9/34 ,  H04L2209/12 ,  H04L2209/24

Abstract: N key generation circuits are arranged in a pipeline having N stages. Each key generation circuit is configured to generate a round key as a function of a respective input key and a respective round constant. Output signal lines that carry the round key from a key generation circuit in a stage of the pipeline, except the key generation circuit in a last stage of the pipeline, are coupled to the key generation circuit in a successive stage of the pipeline to provide the respective input key.