公开(公告)号：US20210288590A1

公开(公告)日：2021-09-16

申请号：US16814626

申请日：2020-03-10

Applicant: XILINX, INC.

Inventor： Junho CHO ,  Kevin ZHENG ,  Parag UPADHYAYA

IPC: H02M7/483

Abstract: An example continuous time linear equalizer (CTLE) includes a first inverter; a second inverter having an input to receive an input signal; a capacitor coupled between an input of the first inverter and the input of the second inverter; a resistor coupled between a common-mode voltage and the input of the first inverter; a third inverter having an output to provide an output signal; and a node comprising an output of the first inverter, an output of the second inverter, an input of the third inverter, and the output of the third inverter.