公开(公告)号：US20230058749A1

公开(公告)日：2023-02-23

申请号：US17867625

申请日：2022-07-18

Applicant: XILINX, INC.

Inventor： Stephan MUNZ ,  Francisco Barat QUESADA ,  Baris OZGUL ,  Javier CABEZAS RODRIGUEZ ,  Zachary DICKMAN ,  Pedro Miguel Parola DUARTE ,  Dylan STUART ,  Juan J. NOGUERA SERRA

IPC: G06F17/16 ,  G06F15/80 ,  H03K19/173

Abstract: Examples herein describe techniques for adapting a multiplier array (e.g., a systolic array implemented in a processing core) to perform different dot products. The processing core can include data selection logic that enables different configurations of the multiplier array in the core. For example, the data selection logic can enable different configurations of the multiplier array while using the same underlying hardware. That is, the multiplier array is fixed hardware but the data selection can transmit data into the matrix multiplier such that it is configured to perform different length dot products, perform more dot products in parallel, or change its output precision. In this manner, the same underlying hardware (i.e., the multiplier array) can be reconfigured for different dot products which can result in much more efficient use of the hardware.

公开(公告)号：US20230059970A1

公开(公告)日：2023-02-23

申请号：US17867630

申请日：2022-07-18

Applicant: XILINX, INC.

Inventor： Francisco Barat QUESADA ,  Baris OZGUL ,  Dylan STUART ,  Stephan MUNZ ,  Zachary DICKMAN ,  Javier CABEZAS RODRIGUEZ ,  David Patrick CLARKE ,  Pedro Miguel Parola DUARTE ,  Peter MCCOLGAN ,  Juan J. NOGUERA SERRA

IPC: G06N20/00

Abstract: Examples herein describe techniques for reducing the amount of memory used during weight sparsity. When decompressing the weights, the uncompressed weight data typically has many zero values. By knowing the location of these zero values (e.g., their indices in a weight matrix), the processor core can prune some of the activations (e.g., logically reduce the size of the activation matrix) which improves the efficiency of the processor core. In embodiments herein, the processor core includes logic for identifying the indices of the non-zero value after decompressing the compressed weights. These indices can then be used to prune the activations to improve the efficiency of the processor core.