公开(公告)号：US20200076424A1

公开(公告)日：2020-03-05

申请号：US16118899

申请日：2018-08-31

Applicant: Xilinx, Inc.

Inventor： Prashant Dubey ,  Sundeep Ram Gopal Agarwal

IPC: H03K17/687 ,  H01L25/065

Abstract: Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.

公开(公告)号：US10826492B2

公开(公告)日：2020-11-03

申请号：US16118899

申请日：2018-08-31

Applicant: Xilinx, Inc.

Inventor： Prashant Dubey ,  Sundeep Ram Gopal Agarwal

IPC: H01L25/065 ,  H03K17/687 ,  H01L27/06 ,  H01L23/48 ,  H01L23/528

Abstract: Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.

公开(公告)号：US11374564B1

公开(公告)日：2022-06-28

申请号：US17067351

申请日：2020-10-09

Applicant: XILINX, INC.

Inventor： Prashant Dubey ,  Sundeep Ram Gopal Agarwal

IPC: H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H03K17/687 ,  H01L27/06

Abstract: Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.