中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.016 seconds)

    POWER GATING IN STACKED DIE STRUCTURES
    1.
    发明申请
    POWER GATING IN STACKED DIE STRUCTURES 审中-公开

    公开(公告)号：US20200076424A1

    公开(公告)日：2020-03-05

    申请号：US16118899

    申请日：2018-08-31

    Applicant: Xilinx, Inc.

    Inventor： Prashant Dubey ,  Sundeep Ram Gopal Agarwal

    IPC: H03K17/687 ,  H01L25/065

    Abstract: Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.

    Softmax circuit
    2.
    发明授权
    Softmax circuit 有权

    公开(公告)号：US10949498B1

    公开(公告)日：2021-03-16

    申请号：US16352764

    申请日：2019-03-13

    Applicant: Xilinx, Inc.

    Inventor： Vijay Kumar Reddy Enumula ,  Sundeep Ram Gopal Agarwal

    IPC: G06F17/16 ,  G06F7/556 ,  G06N3/04

    Abstract: Disclosed approaches for circuitry that implements a softmax function include difference calculation circuitry configured to calculate differences between combinations of elements, zk−zj, of a vector. First lookup circuitry is configured to lookup and output representations of exponential values, ezk−zj associated with the differences in response to input of the differences. Each adder circuit of N adder circuits sums a subset of the exponential values output from the first lookup circuitry and a value of 1. The sum output by each adder circuit denotes a denominator of a plurality of denominators of the softmax function. Second lookup circuitry is configured with quotients and looks-up and outputs quotients associated with the plurality of denominators as results of the softmax function.

    Programmable termination circuits for programmable devices
    4.
    发明授权
    Programmable termination circuits for programmable devices 有权

    公开(公告)号：US10998904B1

    公开(公告)日：2021-05-04

    申请号：US16686073

    申请日：2019-11-15

    Applicant: Xilinx, Inc.

    Inventor： Sundeep Ram Gopal Agarwal ,  Brian C. Gaide ,  Ramakrishna Kishore Tanikella

    IPC: H03K19/00 ,  H01L25/065

    Abstract: Configurable termination circuits for use with programmable logic devices are disclosed. In one implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to a fixed voltage. In another implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to an output of the one or more configurable logic blocks. In some implementations, the programmable logic device may include a platform management controller to configure the termination circuits based on configuration data.

    Power gating in stacked die structures
    5.
    发明授权
    Power gating in stacked die structures 有权

    公开(公告)号：US10826492B2

    公开(公告)日：2020-11-03

    申请号：US16118899

    申请日：2018-08-31

    Applicant: Xilinx, Inc.

    Inventor： Prashant Dubey ,  Sundeep Ram Gopal Agarwal

    IPC: H01L25/065 ,  H03K17/687 ,  H01L27/06 ,  H01L23/48 ,  H01L23/528

    Abstract: Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.

    Programmable pipeline at interface of hardened blocks
    6.
    发明授权
    Programmable pipeline at interface of hardened blocks 有权

    公开(公告)号：US10990555B1

    公开(公告)日：2021-04-27

    申请号：US16735358

    申请日：2020-01-06

    Applicant: XILINX, INC.

    Inventor： Aashish Tripathi ,  Sundeep Ram Gopal Agarwal

    IPC: G06F13/40 ,  G06F13/20

    Abstract: Embodiments herein describe an interface between PL fabric and a hardened block that includes a programmable pipeline. This pipeline includes at least a sequential element and a bypass path. For time critical nets in a netlist, the programmable IC routes a net through the sequential element. Doing so mitigates or eliminates the uncertainty associated with routing the net from the hardened block through PL fabric. Also, the sequential element can increase the available time for capturing the data. For less time critical nets, the net can route through the bypass path. This means the route from the hardened block to the PL fabric is determined on the fly by a routing algorithm rather than being fixed.

    Power gating in stacked die structures
    10.
    发明授权
    Power gating in stacked die structures 有权

    公开(公告)号：US11374564B1

    公开(公告)日：2022-06-28

    申请号：US17067351

    申请日：2020-10-09

    Applicant: XILINX, INC.

    Inventor： Prashant Dubey ,  Sundeep Ram Gopal Agarwal

    IPC: H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H03K17/687 ,  H01L27/06

    Abstract: Examples of the present disclosure provide power gating for stacked die structures. In some examples, a stacked die structure comprises a first die and a second die bonded to the first die. In some examples, a power gated power path is from a bonding interface between the dies through TSVs in the second die, a power gating device in the second die, and routing of metallization layers in the second die to the circuit region in the second die. In some examples, a power gated power path comprises a power gating device in a power gating region of the first die and is configured to interrupt a flow of current through the power gated power path to a circuit region in the second die.

Patent Agency Ranking