公开(公告)号：US20250077243A1

公开(公告)日：2025-03-06

申请号：US18242246

申请日：2023-09-05

Applicant: XILINX, INC.

Inventor： Mohan Marutirao DHANAWADE ,  Ramakrishna Ganeshu POOLLA ,  Ahmad R. ANSARI

IPC: G06F9/448

Abstract: Some examples described herein provide for instruction glitch protection in an integrated circuit. In an example, a method includes generating a random number by the integrated circuit. The method also includes identifying, based at least in part on the generated random number, a sequence from a set of sequences stored in a memory of the integrated circuit, each sequence of the set of sequences corresponding to an order of execution for a plurality of tasks. The method further includes performing, by the integrated circuit, each task of the plurality of tasks in the order of execution corresponding to the identified sequence.

公开(公告)号：US20240220365A1

公开(公告)日：2024-07-04

申请号：US18090207

申请日：2022-12-28

Applicant: XILINX, INC.

Inventor： Ramakrishna Ganeshu POOLLA ,  Bharath MULAGONDLA ,  Felix BURTON ,  Mohan Marutirao DHANAWADE

IPC: G06F11/14 ,  G06F9/4401

CPC classification number: G06F11/1417 ,  G06F9/4401 ,  G06F2201/805

Abstract: Error and debug information is saved during a boot process. A read only memory (ROM) debug circuitry (RDC) obtains detected errors within ROM code during a boot process. Error information is generated and stored within a first memory element. The error information includes entries. Each of the entries is associated with a respective one of the errors. Debug information is generated and stored by the RDC within a second memory element. The debug information is associated with the boot process. Further, the method includes outputting, via test circuitry of the processing system, the error information and debug information based on a testing instruction.