公开(公告)号：US20230229757A1

公开(公告)日：2023-07-20

申请号：US17578292

申请日：2022-01-18

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  James MURRAY ,  Stefano STABELLINI

IPC: G06F21/53 ,  G06F9/455

CPC classification number: G06F21/53 ,  G06F9/45558 ,  G06F2009/45587 ,  G06F2009/45579

Abstract: Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.