公开(公告)号：US20240111693A1

公开(公告)日：2024-04-04

申请号：US17957418

申请日：2022-09-30

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD ,  Sarosh I. AZAD ,  Pramod BHARDWAJ ,  Yanran CHEN ,  James MURRAY

IPC: G06F13/16 ,  G06F11/07

CPC classification number: G06F13/1631 ,  G06F11/0772 ,  G06F13/1668

Abstract: Techniques to provide transaction redundancy in an IC include receiving an original memory access request directed to a first memory aperture, constructing a redundant memory access directed to a second memory aperture, and selectively returning a response of the first or second memory aperture to an originator based on contents of the responses. For a write operation, if acknowledgement indicators of the responses indicate success, a response is returned to the originator. For a read operation, if acknowledgement indicators of the responses indicate success and data returned in the response match one another, a response is returned to the originator. If the acknowledgement indicators indicate success, but the data does not match, a retry of the original and redundant read requests is initiated. If any of the acknowledgement indicators do not indicate success, an error is declared. In a mixed-criticality embodiment, the redundant memory access request may be constructed selectively.

公开(公告)号：US20230229757A1

公开(公告)日：2023-07-20

申请号：US17578292

申请日：2022-01-18

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  James MURRAY ,  Stefano STABELLINI

IPC: G06F21/53 ,  G06F9/455

CPC classification number: G06F21/53 ,  G06F9/45558 ,  G06F2009/45587 ,  G06F2009/45579

Abstract: Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.

公开(公告)号：US20230094621A1

公开(公告)日：2023-03-30

申请号：US17449561

申请日：2021-09-30

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  James MURRAY

IPC: G06F12/0817

Abstract: Embodiments herein describe memories in a processor system in an integrated circuit (IC) that can be assigned to either a cache coherent domain or an I/O domain, rather than being statically assigned by a designer of the IC. That is, the user or customer can assign the memories to domain that best suits their desires. Further, the memories can be reassigned to a different domain if the user later changes her mind.