公开(公告)号：US20240163092A1

公开(公告)日：2024-05-16

申请号：US17985736

申请日：2022-11-11

Applicant: XILINX, INC.

Inventor： James D. WESSELKAMPER ,  Thomas Paul LEBOEUF ,  Steve E. MCNEIL ,  Jason J. MOORE ,  James ANDERSON

IPC: H04L9/08 ,  H01L23/00 ,  H01L25/18

CPC classification number: H04L9/088 ,  H01L23/576 ,  H01L25/18 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: Stacked integrated circuit devices, chip packages and methods for operating a chip package are described herein that provide an increased level of backside protection from physical attacks that could compromise confidentiality or authentication of the integrated circuit device. In one example, a chip stack includes a sacrificial integrated circuit (IC) die stacked with a primary IC die. The sacrificial IC die includes a first split key information source. The primary IC die has security circuitry configured to generate an encryption key based at least in part on first split key information transmitted from the sacrificial IC die across a die-to-die interface to the primary IC die. Separation of the dies to probe or modify of the primary IC die would cause the destruction of split key information required to operate the functional circuitry of the primary IC die.

公开(公告)号：US20250111765A1

公开(公告)日：2025-04-03

申请号：US18374639

申请日：2023-09-28

Applicant: XILINX, INC.

Inventor： Thomas Paul LEBOEUF ,  James ANDERSON ,  James D. WESSELKAMPER ,  Jason J. MOORE

IPC: G08B13/22 ,  G11C19/28 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

Abstract: An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.