公开(公告)号：US20240163092A1

公开(公告)日：2024-05-16

申请号：US17985736

申请日：2022-11-11

Applicant: XILINX, INC.

Inventor： James D. WESSELKAMPER ,  Thomas Paul LEBOEUF ,  Steve E. MCNEIL ,  Jason J. MOORE ,  James ANDERSON

IPC: H04L9/08 ,  H01L23/00 ,  H01L25/18

CPC classification number: H04L9/088 ,  H01L23/576 ,  H01L25/18 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: Stacked integrated circuit devices, chip packages and methods for operating a chip package are described herein that provide an increased level of backside protection from physical attacks that could compromise confidentiality or authentication of the integrated circuit device. In one example, a chip stack includes a sacrificial integrated circuit (IC) die stacked with a primary IC die. The sacrificial IC die includes a first split key information source. The primary IC die has security circuitry configured to generate an encryption key based at least in part on first split key information transmitted from the sacrificial IC die across a die-to-die interface to the primary IC die. Separation of the dies to probe or modify of the primary IC die would cause the destruction of split key information required to operate the functional circuitry of the primary IC die.

公开(公告)号：US20250007724A1

公开(公告)日：2025-01-02

申请号：US18215140

申请日：2023-06-27

Applicant: XILINX, INC.

Inventor： James ANDERSON ,  Aman GUPTA ,  James D. WESSELKAMPER

IPC: H04L9/32

Abstract: Techniques for network-on-chip (NoC) memory addressable encryption and authentication. In an embodiment, NoC circuitry includes NoC routing circuitry, memory circuitry that stores a security parameter, and security circuitry that secures (e.g., encrypts and/or authenticates) a payload based on the security parameter. The security circuitry may secure the payload before the payload is packetized for transmission through the NoC, after the payload is de-packetized for output to an endpoint, or as the payload transits the NoC. The security circuitry may be centralized or distributed amongst access points of the NoC. Distributed security circuitry may exchange a security parameter over a secure link of the NoC circuitry. The security circuitry may include decryption circuitry that decrypts a response from a first endpoint before the response is packetized for transmission through the NoC, after the response is de-packetized for output to a second endpoint, or as the response transits the NoC.

公开(公告)号：US20240281537A1

公开(公告)日：2024-08-22

申请号：US18111808

申请日：2023-02-20

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  James D. WESSELKAMPER ,  James ANDERSON ,  Nader SHARIFI ,  Ahmad R. ANSARI ,  Sagheer AHMAD ,  Brian C. GAIDE

IPC: G06F21/57 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  H04L9/30

CPC classification number: G06F21/575 ,  H04L9/0618 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/14 ,  H04L9/30 ,  G06F2221/034

Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.

公开(公告)号：US20250111765A1

公开(公告)日：2025-04-03

申请号：US18374639

申请日：2023-09-28

Applicant: XILINX, INC.

Inventor： Thomas Paul LEBOEUF ,  James ANDERSON ,  James D. WESSELKAMPER ,  Jason J. MOORE

IPC: G08B13/22 ,  G11C19/28 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

Abstract: An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.